Home > Products > Methodology Core-to-Core Methodology Advances in I/O drivers, packages, and PCBs are failing to keep pace with transistor scaling. Variables such as process, temperature and voltage variation; and issues including simultaneous switching noise, crosstalk, and intersymbol interference create significant design challenges. SiSoft created the industry's most rigorous methodology to effectively address these issues. Core-to-Core establishes the required framework necessary to design, simulate, and analyze high-speed silicon and systems. Key features of Core-to-Core include: Library Validation IO Model Characterization Solution Space Analysis Automated Waveform Processing Automated Timing Analysis IO Buffer Models Design Analysis Reuse Results Reporting Library Validation - A validated library is the foundation of any design and as such, the quality of the input dictates the quality of the result. A design incorporates many types of information; including the simulation models, timing models, design netlist, and allowed transfers. Each of these pieces of information is interrelated and the methodology needs to ensure consistency between them. Differences must be reported. IO Model Characterization - IO cell specifications give only a partial view of how an IO cell operates. These specifications are developed with a set of assumptions based on the cell use and input conditions. Core-to-Core specifies the examination of the IO over a range of frequencies, slew-rates, and input amplitudes. Data captured from these simulations is then used to define the limits of operation for an IO. These limits must be codified into a waveform and timing analysis tool (Quantum-SI for instance) to ensure that device assumptions are not violated in the actual design environment. Solution Space Analysis - In the design phase, each net class must be explored with regard to variation of etch length, impedance, topology, termination, driver type, stimulus, and ac noise. In addition, this analysis needs to support both uncoupled and coupled simulation. From this data, the actual design limits of operation and the rules for layout are derived. Automated Waveform Processing - Given the large range of variables that need to be analyzed and the fact that each simulation may contain a large number of edges (for instance, to excite ISI and support coupling analyses), manual review of the simulations is nearly impossible. The Core-to-Core methodology prescribes automated waveform rules analysis and timing extraction. Automated Timing Analysis - As with waveform analysis, the large numbers of simulations make manual (or even script based) data extraction difficult. The methodology establishes a means of extracting the timing information from the simulations and applies the appropriate source/target/clock data to determine setup and hold margins. Detailed analysis of each network class needs to be reported. IO Buffer Models - Simulation models for signal integrity investigations are available in transistor level and behavioral formats. Behavioral allows the fastest simulation times, but transistor level models are often required for design accuracy. Models are usually available in only one of these two formats. In any case, the methodology allows seamless support of any combination of transistor and behavioral models. Design Analysis Reuse - Many projects are followed by speed-ups, mid-life kickers, vendor process changes, or design repackaging projects. These follow-on projects generally utilize most of the devices found in the original design, but may boost frequency or add additional system functionality. Re-use of the design library and major pieces of the design analysis description data allows these new projects to be completed more quickly. By utilizing the initial Core-to-Core steps, serial or parallel development projects are automatically supported. Results Reporting - How data is reported is critical. The methodology outlines a means to allow the designer to view design results in the detail that they need to solve a problem. Reports that summarize various views (roll ups) of the data to reports that provide explicit detail on every edge of every simulation are required and is a process called Progressive Discovery.      Home | Contact © 2002-2008 Signal Integrity Software, Inc.