Multi-Gigabit Serial Link Design

Multi-Gigabit Serial Link Design
As serial link speeds increase, eyes close at the receiver input and active equalization circuitry is needed inside the receiver to recover a usable signal. The behavior of the receiver's equalization and clock recovery behavior must be analyzed over tens of millions of bits to get a reasonable estimate of the link's Bit Error Rate (BER) Quantum Channel Designer combines time-domain, frequency domain and statistical techniques to provide support for this new class of designs.

QSI Datasheet (PDF)

High Speed Parallel Interface Design

High Speed Parallel Interface Design
Quantum-SI integrates timing, signal integrity and crosstalk analysis to provide true high speed design closure for system, FPGA and ASIC designs.
Quantum-SI Design Kits give you a head start on your design cycle by offering pre-scrubbed and pre-integrated static timing and signal integrity models for popular standard interfaces, in addition to detailed documentation. Quantum-SI Design Kits allow you to start simulating immediately, and can be readily adapted to your design's specific requirements.

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From Our Customers:

“The combination of SiSoft’s modeling expertise and Altera’s intricate understanding of advanced transceiver technology allow us to deliver highly accurate, high-performance IBIS-AMI models to our customers.  With these models, the complex circuit components in our devices can be rapidly simulated to represent highly accurate serial link performance.”
Bernhard Friebe
Senior Product Marketing Manager, High-end FPGAs

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