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Overview |
Pre-/Post-Layout Analysis |
Analysis Results |
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New in 2007.08
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Quantum-SI™ Overview
Quantum-SI is the recognized leader for high-speed design among electrical and signal integrity engineers,
with a proven track record for addressing tough high speed design problems.
Quantum-SI's comprehensive analysis capabilities
accurately predict system-level noise and timing margins while significantly reducing the time
and effort required to perform analysis with traditional methods. Quantum-SI's
"interface-centric" analysis approach allows engineers to
quickly and easily analyze an entire design for the composite effects of signal integrity, crosstalk and timing
and achieve first pass success. Quantum-SI's advanced data and simulation
management allows designers to easily simulate and manage thousands of simulations.
Integrated Signal Integrity and Timing Analysis
Quantum-SI provides a truly integrated solution for signal integrity and timing analysis of
complex high-speed multi-board systems.
- Quantum-SI implements a methodology that encompasses pre-layout and post-layout simulations with rigorous
waveform processing, automatically extracting waveform quality reports and interconnect delays.
- Extracted interconnect delays are utilized by static timing analysis for both synchronous
and source-synchronous designs.
- Quantum-SI provides the flexibility to perform all signal integrity and timing analysis at
either the core of the chip, the pad of the I/O, or the pin of the package of both the
source and target components.
Timing Analysis, Waveform Quality, and Eye Diagram Processing
Interface-centric Analysis
Quantum-SI capture the different signal classes in a high speed
interface and their required timing relationships. Quantum-SI uses this
information to drive how timing and signal integrity analyses are performed.
Traditional tools perform signal integrity analysis only, leaving timing
analysis and the integration of signal integrity and timing data up to the user.
Quantum-SI uses net-class specific information to drive signal integrity
analysis, using appropriate data rates and stimulus patterns. Interconnect
delays are extracted from signal integrity simulations and are combined with the
timing model to determine timing margins for all the required timing
relationships in the interface.
Core-to-Core™ Methodology
SiSoft has developed a formalized end-to-end analysis methodology, known as Core-to-Core™,
which includes a highly automated process for analyzing signal integrity, crosstalk and timing from the inputs of
output buffers to the outputs of input buffers and all the electrical interconnects in between. This methodology is
implemented in the Quantum-SI pre-/post-layout analysis flows. Quantum-SI is the only product that completely integrates
these complex analyses in a single solution allowing engineers to achieve High-Speed Design Closure.
Rigorous Waveform Processing
Quantum-SI offers the industry's most rigorous waveform and eye diagram analysis, processing every edge
of every waveform, across the entire solution space. With over 18 measurement levels, and
the ability to uniquely specify both rising and falling parameters, only Quantum-SI allows
engineers to process the most advanced I/O structures and accurately assess the true waveform
quality and timing margins in a design.
Waveform Processing Levels
HSPICE® Integration
Quantum-SI 100 and higher product configurations provide a seamless interface to the HSPICE simulation engine,
which includes support for native HSPICE and HSPICE/IBIS simulation including encrypted HSPICE models. Quantum-SI
automatically generates and submits appropriate Spice netlists and processes the simulation results for waveform
quality and interconnect delays. Quantum-SI can submit HSPICE-based simulation decks locally or to queuing systems,
such as LSF, to maximize compute resource utilization.
Seamless Support of IBIS and HSPICE® Models
Quantum-SI supports the inclusion of both HSPICE and IBIS models through an extended IBIS
syntax. This allows for simulation with transistor level and behavioral (IBIS) models as well as
the inclusion of any supported HSPICE element.
Quantum-SI's Spice/IBIS Simulator
Quantum-SI includes an internal Spice/IBIS simulator that provides high performance extremely accurate simulation
for IBIS I/O buffers. The Quantum-SI simulation engine includes support for standard Spice elements, including subcircuits
and lossy transmission-lines.
Design Analysis Reuse
Design analysis reuse is defined as the ability to reuse design analysis environments
within an implementation, across different physical implementations, and between pre-layout and
post-layout analysis. Quantum-SI provides analysis reuse by utilizing the transfer net data structure (similar to a net class).
This unique capability allows SiSoft to offer pre-configured Quantum-SI design analysis kits that are ready to simulate out-of-the-box
for signal integrity, crosstalk, and timing. These kits have been proven to shave weeks to months off of the traditional analysis cycle.
Transfer Netlist
The transfer net is an implementation independent network description and serves as the primary
data structure for Quantum-SI. It is similar in concept to a net class, but includes key
information about component connectivity, component transfers, operating frequency, and
measurement points. The transfer net construct is the key to tight integration between
pre-layout and post-layout and is instrumental for design analysis reuse.
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