Slash Analysis Time and Costs with Quantum-SI Design Kits

SiSoft works directly with semiconductor companies and customers to produce design analysis kits for Quantum-SI. Quantum-SI design kits allow an interface configuration to be fully analyzed for signal integrity and timing effects. Each kit includes timing and signal integrity models that are pre-scrubbed and pre-integrated, topologies for each different net class / transfer net, and detailed documentation. These kits can save weeks to months off of a traditional analysis cycle by providing preconfigured analysis environments that are ready to run immediately.

Quantum-SI Architectural Design Kits

These kits include generic timing and signal integrity models. Device timing is based either on industry standard specifications or typical budgets for that interface class. Signal integrity models are based on representative package parasitics and buffer models from Quantum-SI's technology model library. Architectural kits are useful in the earliest phases of the design cycle, when specific components have not been selected and device timing and signal integrity targets need to be defined based on system level analysis. Architectural design kits also serve as templates for developing more detailed design kits - generic models can be replaced by specific component models as the design progresses.

Quantum-SI Implementation Kits

These kits include timing and signal integrity models for specific component combinations . Component datasheet timing specifications are based on specific loading and measurement conditions - the details of those specifications drive how signal integrity interconnect delay simulations must be performed and measured. In each Quantum-SI Implementation Kit, SiSoft's experts have extracted relevant device timing parameters from the device datasheet, created the pin-specific device timing model, and ensured that the corresponding signal integrity device model contains the correct reference loads, measurement thresholds and input slew rate derating data. Quantum-SI Implementation Kits are complete pin-specific analysis setups that allow users to begin entering their design-specific data and simulating immediately. Because the device models in these kits are pin-specific, Implementation Kits can also be used for post-layout analysis of the user's design database.

Quantum-SI Validation Kits

These kits build on implementation kits by providing a complete pre- and post-route analysis environment for a specific PCB design. These kits can be provided by Semiconductor vendors as a proof statement their device operates at documented speeds with positive design margins. The Validation Kit can include data for the vendor's reference board design, enabling customers to "design-in" the device using the reference board as an example. As users adjust routing lengths for their own unique environment, Quantum-SI performs signal integrity and timing analysis, providing design margins for the user's design. Users can easily replace the reference board data in the Validation Kit with their own PCB data, directly leveraging the kit for post-route analysis.

Advanced Kit Capabilities

Quantum-SI design kits leverage Quantum-SI's powerful capabilities for automating repetitive analysis tasks. Key aspects of how an interface should be modeled and analyzed can be captured in the design kit, with Quantum-SI using this information to drive how SI analysis and timing analysis is performed. Typical examples include:

• Automated Model Management - Technologies that use on-die termination to minimize reflections require multiple simulation models to represent different device behaviors (driving vs. receiving, terminating vs. non terminating, different termination values). This can be supplied using multiple I/O buffer models (common for IBIS models), or through the use of a single I/O buffer model with multiple control states (common for transistor-level SPICE models). The models used for an individual simulation can differ depending on which bus transaction is being simulated (i.e. which device is driving, and which device is receiving). Quantum-SI design kits capture the model setup used to simulate each different data transaction, allowing automatic management of simulation model assignments during simulation.
• Input Slew Rate Derating - High speed technologies like DDR2/DDR3 can have timing margins of 100ps or less, where correct integration of SI and timing analysis is crucial. These technologies change the device's specified setup and hold time requirements based on the slew rate of signals at the device's input pins. Quantum-SI automates measurement of input slew rates and the corresponding adjustments to the device timing budget. Slew rate derating data is included in device models supplied with Quantum-SI design kits - automating the entire process from the user's point of view. Analysis details - measured slew rates and their corresponding impact on timing budgets - are documented in the analysis reports produced by Quantum-SI.
• Population Support - A PCB design is often required to work with many different plug-in memory configurations and multiple memory vendors. Depending on the type of memory module used and which slot it is plugged into, loading (and therefore signal quality) can vary substantially. Being able to automatically analyze different memory populations is important, because each change to the design needs to be analyzed across all possible populations. Quantum-SI design kits can include pre-defined memory populations that the tool will analyze automatically. Populations in the design kit can be readily changed by the user to reconfigure existing cases or add new ones.

Sample DDR2 SoDIMM Kit

Quantum-SI ships with a sample Implementation Design kit that supports DDR2 analysis with JEDEC configurations for 1 and 2 slot SoDIMM modules. This pre-layout analysis environment includes:

• Parameterized topologies for each one slot and two slot SoDIMM configuration utilizing JEDEC raw cards A, B, C and D
  
• Net classes (Transfer nets)
  
• SiSoft parts
  
• IBIS and timing models for DDR2 SDRAM memory devices from Micron Technology, Inc. ("Micron")
  
• IBIS and timing model for a generic memory controller
  

The sample kit is ready-to-use and can be easily reconfigured to meet your specific specific requirements. It allows signal integrity and timing analysis to be quickly performed over process, voltage and temperature conditions for a wide range of parametric variations. In addition, on die termination (ODT) and slew rate derating are performed automatically and all DDR2 waveform processing levels are supported.

• View DDR2 SoDIMM Kit Documentation
• More information from Micron Technology, Inc.

For more information, contact sales@sisoft.com.