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SiSoft Webinars
These live web broadcasts discuss contemporary design issues and how SiSoft's
tools can be used to address them. Webinars are broadcast live and
recorded for later replay.
Request a link for replay of a previously broadcast SiSoft webinar
Request to be invited to future SiSoft webinars
"Designing with DDR3" - January, 2008
DDR3 specifications call for operating speeds of 800-1600 MT/s with timing
margins well under 100ps. Tight control of PCB layout is mandatory and detailed
timing / SI analysis is required to ensure adequate design timing and voltage
margins.
DDR3 presents new high-speed design challenges since controllers can vary their
output timing dynamically using a process known as “write leveling”. This
simplifies board-level routing but can complicate high-speed design analysis,
since signal integrity and timing analysis must now be performed on a per-lane
basis.
Successful DDR3 design requires an integrated approach to system-level timing
and signal integrity that models detailed signal behavior and reduces analysis
integration error to a minimum. This requires a comprehensive understanding of
component timing specifications and a corresponding set of simulation
strategies.
This Webinar focuses on the following topics:
- DDR3 module “fly-by” routing; implications for timing / SI analysis
- New signal quality requirements for DDR3
- SiSoft’s programmable DDR3 controller timing model
- Integrated DDR3 timing/signal integrity flow
- SiSoft Architectural/Validation Design Kits for DDR3 Design
"Bowling for Picoseconds" - June, 2007
DDR2 designs now operate at speeds of 800 MT/s, with timing margins in the
sub-100ps range. At these speeds, tight control of PCB layout is mandatory
and detailed timing / SI analysis is needed to ensure design margins are
properly centered. DDR2 component timing specifications document the exact
conditions under which device timing is measured and guaranteed. These
specifications are complex, varying based on device pin class, operating speed,
rising vs. falling edge and input slew rate.
Determining interface margin to the sub-100ps level requires making detailed
signal integrity interconnect delay measurements based on how component timing
is specified. Those interconnect delay measurements must then be properly
integrated into a timing model for the overall interface. This is simple
in concept but difficult in actual practice.
This Webinar focuses on the following topics:
- DDR2 component timing specifications and measurement conditions
- Normalizing SI analyses to produce interconnect delays suitable for
inclusion into interface timing models
- Differences between DDR2 and DDR3 architectures; implications for timing
/ SI analysis
© 2002-2008 Signal Integrity Software, Inc.
