Papers & Presentations

• Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard (paper) - DesignCon 2008
• Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard (presentation) - DesignCon 2008
• Counting the Picoseconds: Integrating Timing, Signal and Power Integrity Analysis (paper) - DesignCon 2008
• Counting the Picoseconds: Integrating Timing, Signal and Power Integrity Analysis (presentation) - DesignCon 2008
• Exploration of Deterministic Jitter Distributions (paper) - DesignCon 2008
• Exploration of Deterministic Jitter Distributions (presentation) - DesignCon 2008
• Multi-Gigabit Serial Link Analysis - Piecing Together a Design and Verification Strategy (paper) - SNUG Boston 2007
• Multi-Gigabit Serial Link Analysis - Piecing Together a Design and Verification Strategy (presentation) - SNUG Boston 2007
• SiSoft's IBIS-AMI Model Evaluation Toolkit - Beijing & Tokyo IBIS Summits, Sept 2007
• IBIS-AMI Modeling Proposal Status Report - Beijing & Tokyo IBIS Summits, Sept 2007
• IBIS-ATM Model Validation - IBIS-ATM task group, July 2007
• IBIS-ATM SerDes Modeling Status Report - DAC IBIS Summit, 2007
• System Level Timing Closure using HSpice (paper)  - SNUG San Jose 2007
• System Level Timing Closure using HSpice (presentation) - SNUG San Jose 2007
• IBIS-ATM Modeling Proposal - DesignCon IBIS Summit, 2007
• IBIS-ATM SerDes Modeling Status Report - DesignCon IBIS Summit, 2007
• An Engineering Hat Trick - DesignCon TecPanel, 2007
• Serial Link Modeling Terminology - IBIS-ATM Sub-committee, 2006
• System Level Timing Closure using IBIS Models - Shanghai/Tokyo IBIS Summits, 2006
• Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems (paper) - DesignCon 2005
• Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems (presentation) - DesignCon 2005
• Can IBIS Accurately Model SSO? - IBIS Summit Oct, 2004
• Establishing Pass Fail Criteria for High-Speed Digital Interfaces - DesignCon 2004
• Signal Integrity and Timing Analysis Simulation Reuse - DesignCon 2004
• IBIS Quality Committee Update - IBIS Summit June 2003
• Practical Use of IBIS Quality Checklist - IBIS Summit January 2003
• Beyond DDR, SiSoft and Timing Analysis of QBM Systems - DesignCon 2003
• High-Speed Design Challenges for a 1.4Ghz Network Processor - DesignCon 2003
• IBIS Quality Committee Report - IBIS Summit October 2002
• SPICE versus IBIS - IBIS Summit October 2002
• IBIS Quality Committee Report - IBIS Summit June 2002
• LVDS IBIS Models @ 1.25GHz - IBIS Summit June 2003
• Source Synchronous Bus Design - DesignCon 2002
• Improving IBIS Quality - DesignCon 2002
• The Bitter-Sweet Experiences of Using IBIS Models - IBIS Summit January 2002
• Solution Space Analysis - DesignCon 2001