Package Design

SiSoft has designed many styles of packages for its customers. Key attributes of our design capabilities include:
  • Experience with package with 2 to 32 layers
  • Wire-bond, TAB, and Flip-chip
  • Cavity up/cavity down designs
  • Ceramic and Organic experience
  • Design experience with >1000 balls
  • Understand commercial and consumer marketplace requirements
  • 2D/3D electromagnetic modeling
  • Power delivery modeling
  • Experienced IC designers
  • Layer count minimization
  • Routing studies
SiSoft focuses on the SI issues that impact chip performance including crosstalk, power delivery, signal return, IC pinout and ball assignment, but we are conscious of the need to balance cost with performance as well as the need to assign/tradeoff budgets between ICs, package, and PCB. SiSoft's experience with full custom IC design allows us to work directly with chip teams to obtain the best pad assignment tradeoffs. Our design capabilities allow us to deliver packages that utilize the minimum number of layers while providing the best overall signaling environment.
 
Data we provide to our customers includes:
  • Layout guidelines documentation
  • 2-D and 3-D models of the package interfaces
  • Simulation environment that exercises the package for SI compliance
While SiSoft usually works directly with a layout designer at the package fabricator, SiSoft can also utilize its own partners to perform the layout. In either case, we work with the IC team, the package layout designer, and our customer throughout the entire process to ensure a high quality package is delivered.

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From Our Customers:

“We have worked closely with SiSoft to develop and correlate our IBIS-AMI models to reference simulations and hardware.  These IBIS-AMI models provide customers with accurate simulation results at speeds more than 100 to 1,000 times faster than traditional simulation methodologies.”
 
Anthony Torza, Senior Product Marketing Manager at Xilinx


Xilinx - IBIS-AMI Models - Simulation Speed
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