Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.

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From Our Customers:

“The combination of SiSoft’s modeling expertise and Altera’s intricate understanding of advanced transceiver technology allow us to deliver highly accurate, high-performance IBIS-AMI models to our customers.  With these models, the complex circuit components in our devices can be rapidly simulated to represent highly accurate serial link performance.”
 
Bernhard Friebe
Senior Product Marketing Manager, High-end FPGAs
Altera


Altera - IBIS Model Development