Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.

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From Our Customers:

"This is the second generation of Virtex technology where we have collaborated with SiSoft to develop and correlate IBIS-AMI models to reference simulations and hardware.  The combination of these IBIS-AMI models and SiSoft’s QCD provides customers with accurate simulation results at speeds more than 100 to 1000 times faster than traditional simulation methodologies, allowing customers to quickly optimize their designs for cost, reliability and performance.”

 Anthony Torza, senior product marketing manager at Xilinx

 



Xilinx - Second Generation Virtex