Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.

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From Our Customers:

"We've worked with SiSoft to create IBIS-AMI models across our SerDes based PHY's in IBM technologies.  SiSoft has demonstrated continued leadership in SerDes modeling by first driving the development of the IBIS-AMI standard and then becoming the leading provider of IBIS-AMI model development, correlation and validation services."
 
Navraj Nandra, Director of Marketing, Analog/Mixed Signal IP, Synopsys


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