Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.

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From Our Customers:

“We are delighted to be working with SiSoft.  As the established leader in the field of system design and analysis for high-speed parallel and serial interfaces and multi-gigabit serial links, SiSoft has enabled us to ensure the signal integrity on all our NFP-32xx high-speed interfaces. By making SiSoft’s technology and capabilities available to our NFP-32xx customers, SiSoft is helping them to accelerate development time while minimizing risks.”
 
Niel Viljoen,
Founder and CEO of Netronome


Netronome - Accelerated Development Time with SiSoft Technology
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