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Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.
To learn more about SiSoft's consulting capabilities, please use the following links:

Technical Staff Interface Experience Quick-Turn SI
Signal Integrity Analysis Crosstalk Analysis Timing Analysis
Technology Assessments SI Design Reviews IBIS Model Generation
Package Design Interconnect Modeling Power Integrity
PCB Design Lab Validation Design Kit Development

To learn more about SiSoft's Training opportunities, please use the following links:

SI Training Methodology and Product Training Jump-Start Training
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