7 Steps to Successful Serial Link Layout, Part 1

Thursday, October 4, 2018

 

Over the past 15+ years I’ve been accumulating a checklist of items required for successful serial link layout. I refer to the list when a customer requests a design review of their implementation, without simulation. The swelling list also regularly appears as an Appendix in reports I write for other customers. So when we began developing our “Pragmatic Signal Integrity” course (often co-taught by SiSoft and SiGuys at DesignCon), I thought “Wouldn’t it be great if I could boil this list down and make it crisp and clean – maybe even ‘7 Steps’?”. It happened. And so what follows is a time-tested collection of items any and every serial link layout needs to work through to be successful.
 

Here’s a quick list of the 7 steps:

1. Minimize Discontinuities

2. Manage Loss

3. Route Using Best Practices

4. Route Using Double-digit Data Rate Best Practices

5. Remove Unacceptable Stubs

6. Prevent Problems Related to Fabrication

7. Engage Firmware Team to Configure SerDes

 

While I wound up with 7 Steps, I could have boiled this down further to only two issues to solve: Loss and Discontinuities. (Or some might say ‘Attenuation and Reflections’, or even the less precise ‘Length and Imperfections’.) Oddly enough, all seven steps work together throughout a design and implementation cycle to manage these two problems from different angles. While I’ll give a more technical explanation of Loss and Discontinuities in another post, here I’ll focus on the mechanics of how they are managed in practice.

 

As I’ve said before, the great thing about Serial Links is their robustness and scalability. Because of this they have become the ubiquitous solution for high-speed data transmission, and many have successfully implemented them without simulation. If you’re approaching the problem from a similar position and simply want to know what must be done in layout, read through this series as we discuss the 7 Steps in detail.

 

Step 1: Minimize Discontinuities

This is where you need to think creatively, and not implement the link in the way it might naturally connect. In short, all unnecessary vias, connectors, breakouts, capacitors, traces, cables, etc. should be removed. Why? Because every transition through another type of interconnect represents another potential “discontinuity”, or element in the connection that can cause an impedance change. And impedance changes cause signal reflections which degrade and distort a signal’s integrity making it harder to recover at its receiving device.

 

It’s not that discontinuities cannot be managed. It’s just that in the larger realm of manufacturing variables and tolerances, the fewer of them you need to manage the better. So learn to look at the link from end to end, find every place the interconnect transitions, and then remove as many transitions as possible. This is the first and best way to minimize discontinuities: decrease the number in the design phase before you’re forced to control them during implementation.

 

If your PCB requires the link to go from one device to another device or connector, you should be able to reduce the diff-pair’s complexity to a stripline trace with vias on each end. With perhaps a short breakout trace on one end (which is potentially another discontinuity). Whatever the case, don’t accept a discontinuity unless it is absolutely required. For example if your layout is tangled and it seems you need extra vias to manage trace crossings, many standards (such as PCIe) allow you to swap the diff-pair connection (connecting p to n and n to p) to simplify layout and hence remove discontinuities. While this would seem to destroy connectivity and confuse polarity, standards have adopted the overhead to discover and correct it in software when the link trains. That in itself tells you it’s important to remove discontinuities.

It may happen that, for the sake of modularity, a design is proposed with three or four connectors in the path. Now it’s time to pushback and ask a few questions. Do we really need all of these? It’s not that connectors can’t be handled – even a few of them – it’s just that they bring more variables and require additional vias. Some connectors are well-designed, introducing a short, understood and consistent impedance. Others are not. And many times it’s the associated vias that are problematic – particularly those used for larger press-fit pins. Either way, if all those connectors are necessary their discontinuities must be understood with regard to their combined impact on signal quality and it’s time to simulate. If a connector is there for orientation instead of modularity, consider using a flex PCB instead. I’d rather bend a signal through a homogeneous medium than send it through the numerous discontinuities associated with a connector.

Once you’ve removed the unnecessary discontinuities, it’s time to match the impedance of the discontinuities that remain. First learn the impedance of your Tx, Rx, any necessary connector(s) and the impedance specified by the standard or protocol you are using. Then minimize the number and magnitude of impedance changes along the path. This normally means using field solvers to calculate and specify the impedance of traces and vias that are of a relevant feature size for your data rate. Via impedance can be tricky to resolve because via solvers are not as readily available on the web as trace solvers. As 85 and 100 Ohms are common impedances for the devices that might be in your path, some choose to interconnect them with 92 Ohms as a way to minimize impedance changes.

 

In effort to minimize discontinuities some route on microstrip trace instead of introducing extra vias and a layer transition to stripline, but that can be problematic. Why? In many situations drill tolerance versus the tolerance of laminated pre-preg layer thickness makes it easier to control via impedance than microstrip trace impedance. When that is true, and manufacturing tolerances are introduced, the microstrip might introduce a larger discontinuity than the via/stripline combination. This phenomenon is fairly well-documented with measured data (pages 16-18). While it’s currently simpler to calculate trace impedance, it’s often simpler to fabricate via impedance.

 

Even when you’ve removed as many discontinuities as possible at the design stage and matched impedances in your implementation, Figure 1 reveals that manufactured impedance of items you expected to have consistent impedance may not turn out that way. Figure 1 is a TDR of a 6.6” trace with two vias and an AC cap; the minimum amount of discontinuities required for this connection. As shown, even though the AC capacitor and its associated pads are fairly well-managed, nuances in the routing and PCB construction cause substantial variations from the intended 100 Ohm impedance. This scenario is explained in more detail on page 14, and reveals discontinuities may still exist even though you removed as many as possible. Which brings us back to where we started: remove all unnecessary discontinuities.

 

 

Figure 1: Measured Discontinuities
 
 

Step 2: Manage Loss

Loss happens, so the challenge is managing and containing it to an acceptable level. And what’s “acceptable” varies dramatically depending on your data rate, protocol, and devices involved. So the first step in managing loss is to find a loss target for your link at the frequencies of interest. This may come from your device’s published Design Guidelines, the Serial Standard in use, rules-of-thumb, SerDes equalization capabilities, or previous projects. SI groups in the larger companies do a good job of making acceptable numbers available for the various interfaces.

In the early days of serial links, loss got all the attention. As such, SerDes equalization is much better at handling loss than discontinuities. And then many low-loss dielectrics began to appear, which are now common and affordable. This led to over-compensation – particularly on short links that didn’t have enough loss to dampen the inevitable reflections explained in the previous section. As such, newer serial standards now specify a range for acceptable loss. So don’t be surprised if your target has both a min and a max.

 

Once your loss target is known, estimate the loss for all your links. If you do not have the tools to do that, your fab vendor can likely help. Just make sure you don’t convert loss to length until you understand your trace construction and materials. The most relevant parameters are loss tangent (Lt, sometimes referred to as Dissipation Factor or Df) and trace width, which directly correlate to dielectric loss and conductor loss, respectively. And if cables are involved the numbers change as well, as they typically have less loss per inch than PCB traces.

 

To understand the relevance of trace construction, Figure 2 reveals a 3x change in insertion loss for 12” of differential PCB trace depending on the materials used. As loss tangents for PCB dielectrics are available through a 10x range (0.002 to 0.02, red to black), dielectric loss is the dominant effect responsible for the ~3x variation in loss. Within each Lt value/color the widths of the differential traces are varied from 3 to 9 mils, which itself causes more than 1 dB variation in loss at 7.5 GHz due to conductor loss. At right we see that widening from 3 to 5 mils significantly reduces conductor loss, while widening beyond 6 mils has less impact.

 
 

Figure 2: 15 Gbps Differential Insertion Loss Variation for 12” of PCB Trace

 

Figure 2 shows a 15 Gbps signal might see anywhere from 1/3 dB per inch to 1 dB per inch, depending on how the PCB traces are implemented. So if your trace loss budget is 15 dB, your max trace length might be anywhere from 15” to 45”. This huge difference illustrates that it is useless to talk about trace length limits until you determine trace construction. Or, looking at it another way, if the length you need to interconnect has too much loss, it’s possible a change in materials will solve the problem.

 

Once you know the dB/inch of your trace construction, you will also want to add in loss for any connectors and vias in the path. If you do not know the loss for these items, a very rough rule-of-thumb below 10 Gbps is to add 0.5 dB for larger ones (e.g., thick backplane vias, right-angle connectors) and 0.25 dB for smaller ones (e.g., 60 mil thick PCB vias, LGA connectors). If you’re above 10 Gbps, double those numbers.

 

While this section has focused on managing “Insertion Loss” (IL, or how much a signal is attenuated as it travels from Tx to Rx), you should be aware that there are other types of loss. Another type of loss getting an increasing amount of attention is “Return Loss” (RL), which quantifies how much of your signal reflects back to the Tx. All serial standards specify a limit for IL, and most specify limits for RL. While RL is more complex to understand and quantify, it is directly related to the magnitude and amount of your discontinuities. As such as you Minimize Discontinuities (Step 1), you are also reducing RL. If your link requires an unreasonable amount of discontinuities, you will likely need to simulate it in order to quantify its RL against your spec’s limits. There is also a loss that quantifies how much energy transfers from differential mode to common mode. While this is even harder to quantify and beyond the scope of our discussion here, the best way to manage it is to do a good job at Step 3: “Route Using Best Practices”.

 

In Conclusion

Here we’ve examined the first two steps in achieving a successful serial link implementation. We’ve belabored them a bit because, again, all the other steps work together to help us contain these same two issues: loss and discontinuities. Serial links have shifted our SI focus from timing skews and signal matching (ala DDRx) because the clock now rides within the data instead of beside it. As such, matching is less critical (except within the diff-pair) and there is generally more freedom in layout as long as loss and discontinuities are understood and managed. Come back for my next post where we’ll discuss the rest of the 7 Steps.

Donald Telian - Guest Blogger, SiGuys 10/4/2018

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