7 Steps to Successful Serial Link Layout, Part 2

Monday, November 5, 2018

Author: Donald Telian, SI Guys - Guest Blogger 

This is a continuation of my previous post detailing the “7 Steps” required to successfully implement a serial link. While all 7 steps aim at controlling discontinuities and loss (concepts introduced in Steps 1 and 2), this post ventures into the pragmatic aspects of managing loss and discontinuities during the routing process. Ever wonder how a tiny via stub can destroy your signal? Read on.

Step 3: Route Using Best Practices

While it would seem self-evident that you need to “route using best practices”, it is worthwhile for us to gaze briefly in this direction. Even though the notion of a “differential pair” has been with us for a long time, the rapid acceleration of serial links and standards around the year 2000 brought diff-pair routing into the mainstream. When the initial serial standards published diff-pair routing do’s and don’ts, the leading layout platforms rushed to implement these “best practices” in software. As such, in today’s world much of what you need to think about in this Step will be forced on you by your layout software.


When thinking about a diff-pair the word “symmetry” should come to mind. It helps to visualize one signal of the pair as a mirror image of the other. For example:

  •  if the “p” side must bend to attach to a capacitor or connector, then bend the “n” side in the same way
  •  when you place a ground via near the p side at layer transitions, place another ground via near the n side at the same location and distance
  •  if the p side must go around a mount hole, make sure the n side also goes around it in similar fashion

These ideas, and others, are what the original diff-pair routing guidelines were made of.

Matching the lengths of the two signals in your diff-pair goes without saying, and will also be enforced by your layout software. While published rules might tell you to match within 5 mils, you’ll probably find your software gets you to within 1 mil. Watch out for those stray route segments hiding within long solder pads, and make sure they’re not summed into only one side of the diff-pair. As data rates increase, the intermediate “phase” must also be managed. Said another way, p/n matching should stay consistent when measured at intermediate points along the path.

Regarding spacing, keep neighboring diff-pairs at least 25 mils away – in the Z direction too. And just like high-speed single-ended nets, always use a solid reference plane for your diff-pairs and don’t route over plane gaps or voids. Finally, over time we’ve learned to not interleave Tx and Rx signals and typically send them to different layers as soon as possible.


Step 4: Route Using Double-digit Data Rate Best Practices

If your interface operates at less than 10 Gbps, feel free to jump to Step 5. Still reading? Good for you, because if you’re not routing for 10 Gbps now you will be soon enough. As such here are some things to do now, or prepare to do soon.


Above 10 Gbps, do not use closely-spaced single-side serpentines shown in Figure 1 (and page 12) to length match because this introduces a substantial discontinuity. Figure 1 shows three routes (above) along with their measured single-ended (blue/gold) and differential (purple) impedance (below). The length-matched trace (gold) causes a significant, albeit narrow, differential impedance discontinuity (purple, between 2 and 2.1 nS). To determine if serpentine segments are too long (and hence too wide in time) for your data rate, have a look at my post on relevant feature size. Spread out your length-match bumps until they become too short to be relevant.


Figure 1: Measured Impedance Discontinuities Caused by Serpentine Routes

Figure 1: Measured Impedance Discontinuities Caused by Serpentine Routes


Also above 10 Gbps, widening traces within large antipads makes an observable improvement in signal quality (page 11). Widening helps reduce the antipad trace segment’s inductance, which increases rapidly when the ground reference is removed. And keep your routes at least two trace widths away from large voids and/or the edge of your reference plane (page 12), again to minimize discontinuities.


Above 20 Gbps NRZ (or 40+ Gbps PAM4) additional routing rules are being added, so always consult new and available routing guidelines. I’ve noticed curvy routing is in fashion, with even more emphasis on phase matching. And strange effects like via cage asymmetries (page 15) will likely be designed out rather than understood and managed in layout. Watch this space.


Step 5: Remove Unacceptable Stubs

The most insidious of all discontinuities has emerged to be the ¼-wavelength via stub. This tiny artifact has the potential to make your signal completely disappear or, more accurately, cancel itself out. As such, an industry that hardly ever re-tools (PCB fabrication, as compared to IC fabrication) has become quite good at “back-drilling” vias to remove problematic via stubs.


As I’ve mentioned in previous posts, Eric Bogatin introduced the helpful rule-of-thumb that predicts the ¼-wavelength PCB stub lengths in inches to be 3/Gbps. While the via stub problem began to accelerate at 6 Gbps, a few years later the vias in 0.250” thick 12 Gbps backplanes became acutely problematic (3/12 = 0.250”) and back-drilling became imperative. So Eric encouraged everyone to play it 10x safe, and keep stubs smaller than 0.3/Gbps. And that is pretty much what happened. The good news is that back-drilling is now commonplace, and hence affordable and reliable.


Figure 2 illustrates the difference between the presence of a ¼-wavelength via stub or a stub that is 10x-shorter, in both eye opening (left) and differential Insertion Loss (IL, right). The plots compare a 12” 12 Gbps channel that includes either a 0.250” (3/12) stub or a 0.025” (0.3/12) stub. As shown, the difference is stunning. While the channel with the shorter stub has a substantial eye opening (upper plot, at left), when the stub lengthens to the critical distance the eye disappears (lower plot, at left). The longer stub causes no eye opening because, as the IL plot (red, at right) reveals, less than 2% of a 6 GHz (12 Gbps) Tx signal arrives at the Rx. In contrast, there is no observable change in loss due to the presence of the shorter stub (green). As predicted by Eric’s rule-of-thumb the 0.250” stub causes the greatest attenuation (loss) at 6 GHz, yet note that nearby frequencies see substantial loss as well. For example at 5 GHz (10 Gbps signal) the loss on the red curve is 2x that of the green. In fact, the loss plots do not become similar until ~600 MHz – which is another expression of the 10x rule.


Figure 2: 12 Gbps Channel with 0.25” Stub or 0.025” Stub

Figure 2: 12 Gbps Channel with 0.25” Stub or 0.025” Stub


Why does the signal disappear? Picture a sinewave splitting in half at the junction where the channel encounters the stub. Half of the signal proceeds down the ¼-wavelength stub until it reaches the end where it is 90° out of phase. At the end of the stub it finds an open circuit causing 100% of the signal to reflect back towards the junction. When the signal arrives back at the stub junction it is 180° out of phase, canceling out the other half of the sinewave on its way to the Rx. As such we see only the lower-frequency components of the signal at the Rx, which looks like noise with no observable 6 GHz eye (Figure 2, left, lower).


While back-drilling is the most common way to remove via stubs, other methods can be used. Those implementing just a few high-speed serial links can solve the problem by keeping signals on outer (or near-outer) layers of the PCB. For example if you breakout of your BGA on the top layer of your 16-layer PCB and via down to layer 15, your resulting stub is likely too small to be of concern. Figure out the resulting stub length and check it against Eric’s rule-of-thumb. Others have chosen sequential lamination as a way to limit via lengths and their stubs to a smaller section of the board’s stackup. Still others use blind and/or buried vias to remove or minimize stub lengths. However you handle it, you definitely need to think 3 dimensionally to ensure via stubs are managed correctly in your layout. You will find it’s helpful to determine your strategy for dealing with stubs before your stackup and signal layers are fully defined.


But vias are not the only cause of stubs. In the early days of serial implementation, some inadvertently caused problematic stubs by adding things like testpoints, ESD devices, or other things to the routes. You wouldn’t do that though, would you? Serial links must be point-to-point, meaning they connect to only one Tx and one Rx. So don’t add anything else. Let’s leave the multiple Tx/Rx problem and its unavoidable stubs to the land of DDR5+. What a messy business that will be.


In Conclusion

While Part 1 of the “7 Steps” detailed the primary serial link challenges (loss and discontinuities), this post has provided a layout-centric view of what must be done during high-speed serial routing. While differential routing methods have become commonplace, be aware that new strategies continue to emerge as frequencies increase. Strategies to deal with problematic stubs are now integral to stackup design and signal layer selection.

With an understanding of the routing challenges and solutions behind us, in the next post we’ll cover Steps 6 and 7 detailing serial link implementation problems that arise in manufacturing and software. Software? Yep, software.

Donald Telian - Guest Blogger, SiGuys 11/5/2018


Response to: 7 Steps to Successful Serial Link Layout, Part 2
Friday, November 16, 2018
Himanshu Modi says:

Great information.

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