Understanding Connector and Package Impedance

Monday, December 9, 2019

Author: Donald Telian, SI Guys - Guest Blogger   

I’ve grown accustomed to viewing passive interconnect as the road signals drive on.  Impedance discontinuities appear as the speed bumps or potholes that make the ride bumpy and unpleasant, if not slower.  Perhaps I’ve looked at too many TDR plots?  For many years our industry has been well-tooled to understand and manage PCB trace impedance, which continues to define the majority of the “road” signals travel on.  Over time higher data rates have caused smaller features to become relevant, requiring us to understand and refine elements we had previously modeled with single-element resistors, capacitors, and inductors.  The bumps were no longer lumps.
 
Around the year 2000, Signal Integrity Engineers began two decades of improvements on via, connector and IC package structures, and models for the same.  Data rates were passing through 1 Gbps, causing the 100 picosecond delay through a typical package or connector to consume more than 1/10th of a UI.  As such, these elements now had to be carefully modeled and designed.  The inherent stubs in vias and their ability to cancel a signal (Step 5) challenged us to quickly understand, model and manage via impedance.   Though connectors and packages were also relevant – sometimes possessing stubs of their own – the development of these models has been slower.  Because these structures are more 3-dimensional than vias, “development” meant numerous things:  formats and accuracy, as well as design and electrical characteristics. 
 
Though connectors and packages have similar lengths and impact on SI analysis, their parameters, vendors, industry dynamics, and hence designs and models have developed differently.  We’ll examine both here, starting with connectors.
 

Connectors, Vendors, and Models

Good connector performance and models is not a given.  Amidst the vast array of parameters a connector vendor juggles, improving electrical performance takes time.  As such, when a connector vendor chooses to enter the high-speed arena I’ve observed them going through phases.  Identifying these phases can be helpful, because determining your connector vendor’s position in this process might be an indicator of the performance you could anticipate from their products.

Here are 5 phases connector vendors and their models typically journey through on the road to “high-speed”:

1. Wake-up Call.  In this phase data rates suggest there should be a model, but it’s not there yet.  Due to lack of planning and/or pressure from customers the development of a good model – and perhaps even good electrical performance – hasn’t happened yet.  If this phase lasts too long it might push the vendor back into delivering lower-speed connections and differentiating on cost rather than performance.  Conversely, if the vendor moves forward into modeling they typically opt for the simpler variety.

2. Simplicity.  Lumped RLC models, RLGC matrices, and SPICE subcircuits dominate this phase.  For intermediate frequencies connector performance does not dictate the performance of the larger interconnects, so these are the models of choice.  While some models struggle with verbosity and SPICE syntax nuances, life is good because there is a deliverable and hence peace between the connector vendor and SI Engineer.  These models tend to be “connector only”, typically lacking characterization of the structures attaching them (e.g., solder, pads, vias, press-fit pin barrels, etc.) - structures thought to be the domain of the customer.  With the advent of good S-parameter tools and skills it became possible to skip this step, moving straight into characterization. 

3. S-Parameter Characterization.  In this phase the simplistic approach and models of the previous phase no longer suffice; connector performance has become a substantial factor in overall system performance.  It’s time for a frequency-rich characterization of not only the connector, but also the structures that surround it.  As it often happens in SI, this phase may have been initiated by savvy customers or unfortunate system failures.  No worries, because VNA (Vector Network Analyzer) and 3D Field Solver vendors suddenly appear to provide the necessary solutions.  Unfortunately no one tells the connector vendor that it will require at least a year to become proficient with these tools, as complexity and configuration nuances become the dividing line between good and bad models.  Furthermore processes and staff to disseminate and support the models must be developed.  One way to tell a vendor is in this phase is they struggle to get an S-parameter model to you, and if you do obtain it you find it imports with low quality metrics, doesn’t simulate well, and may forget to tell you the port assignments.  While this may not endear you to the connector itself, I am thankful to see vendors moving through this phase and hence do my best to provide constructive feedback.

4. Optimization.  Once the characterization becomes reliable, it leads to the optimization of a connector’s attachment structures and the connector body itself.  Use of the tools transitions from modeling what “is” to what “could be”, causing new and relevant discoveries.  Application notes capture useful information, and implementation improvements such as via anti-pad shapes and ground plane cutouts are relayed to the customer.  Optimization of the connector body causes new revisions and/or products.  Because modifications require tooling and time, physical parameters inherent in the design might constrain performance for a while.  But at least the connector’s effects are well-characterized, allowing us to quantify performance limitations while we work on creative workarounds (pages 21-22).  A tell-tale sign the connector or vendor is in this phase is receiving multi-port S-parameter models that import correctly with high quality metrics, yet when you plot its TDR you see substantial impedance bumps and dips.  Not to worry, better performance will be on its way soon enough. 

5. Performance.  Give a connector vendor enough time in the previous phase and higher-data-rate connectors appear with exceptional performance.  I look at the new TDRs and smile, knowing substantial mechanical barriers have been overcome to achieve the observed electrical performance.  This is good news, but the downside is the connectors become more proprietary and second sources are harder to find.  While patents and court filings endeavor to protect the vendor’s position, we enjoy good models, solutions and performance.  Welcome to the dichotomies of the leading edge.

As a connector vendor moves through these phases they hire an increasing number of SI Engineers.  In fact, there’s a good chance you are one of them.  This new array of talent provides not only good products and models; it also empowers a vendor to differentiate with services, consulting, and the ability to help define the next great thing.  What began as simplistic lumped models has morphed into key partnerships and industry leadership with its commensurate obligations and privileges. 

Now that we’ve looked at connectors and their vendors at a high level, let’s venture into their lower-level Ohms-for-picoseconds impedances and discontinuities.

Connectors and Discontinuities

The world of connectors is vast; everything from my home’s HVAC unit to my car to my smartphone is packed full of them.  The array of connector vendors, types, applications, data rates, form-factors, electrical, mechanical, and reliability specifications can make connectors hard to generalize.  Yet from an SI perspective, viewing connectors and their associated PCB attachments in terms of impedance versus time (as in a TDR plot) simplifies things.  Indeed, a good S-parameter measurement or model tells all. 

I primarily view a connector by the discontinuities, or impedances, it presents.  While a connector also imposes “loss”, in most cases it is its discontinuities that are problematic.  In other words, I focus more on Return Loss (RL, signal reflection) than Insertion Loss (IL, signal attenuation).  Some connector datasheets provide both, yet sometimes RL is only visible in a connector’s model.

By definition, RL and IL are inter-related.  In simple terms a signal either reflects off something or goes through it, and RL and IL quantify these effects, respectively.  Our industry and technologies primarily focus on IL because it is a bit simpler, more additive, and was the dominate property in the long-reach interconnects we had to resolve.  As integration makes things smaller, shorter and faster, RL is getting more attention.  In particular, when I see a short connection using a connector with a high RL I get concerned.  The interesting thing is that, while we wouldn’t add RL to improve IL, we can add IL to improve RL – conceptually like fixing ringing with damping.  Let me explain with an example. 

A typical connector has a length around ½”, delays from 50 to 150 ps, and a target impedance of 100 Ohms.  Due to its inherent mechanics (the rigidity required to connect and disconnect reliably), short non-ideal impedances are present.  Depending on where the vendor is in the characterization/optimization cycle described above, these impedances might be substantial or well-managed. 

To study the effects of a connector’s discontinuities on system performance I developed a simple one-connector interconnect.  I modeled the “100 Ohm” connector with variable length discontinuities of both 70 and 120 Ohms separated by 100 Ohm segments, allowing the discontinuities to grow and shrink while holding the total connector length to ½”.  The end result is a system model with a connector that presents discontinuities of different lengths, flanked by variable-length PCB traces (loss tangent = 0.01).  Figure 1 is a TDR plot showing the connector’s discontinuities set to 75 mils, surrounded by PCB traces with lengths from 1” to 5” (varying colors, red to orange).  Note that as the PCB lengths surrounding the connector become longer, the magnitude of the discontinuities “seen” by the Tx becomes smaller.  

 


                Figure 1:  TDR of Connector with 75 mil discontinuities between PCB traces of 1” to 5”

 

While Figure 1 views the connector in terms of its impedances, Figure 2 illustrates how these discontinuities relate to Return Loss (RL).  The X axis plots the length of the PCB traces while the colors represent connector discontinuity lengths, ranging from 25 to 200 mils.  “RL Margin” is shown on the Y axis in relation to a -10dB mask, causing values below the horizontal 0dB line to represent RL values greater (worse) than 10dB.  Measuring against this industry benchmark causes negative values Y values to be “bad” while positive values are increasingly “good”.  As might be expected, as the discontinuities become smaller (vertically, towards purple) the RL margin becomes greater.  What is not as intuitive, yet clearly visible in Figure 2, is that as the PCB traces become longer RL margin also improves because we are damping the effects of the connector.

 


               Figure 2:  RL Margin versus Connector Discontinuity and PCB Lengths.

The vertical line in Figure 2 shows where RL margin becomes positive.  Experience suggests, as is true in this simplistic scenario, if and when a problematic discontinuity can be damped by about 3” of PCB trace both RL and eye margins improve.  While this generalization depends on the magnitude of the discontinuities, the loss tangent of the PCB and other factors, you might be surprised to discover the range of scenarios where it holds true.  For a more complex system example see pages 15-20 in this DesignCon paper.  In other situations it is the vias required to attach a connector that limit performance (pages 13-16), even though the impedance of the connector body itself might be good.  These examples underscore my previous point that connector issues are more related to their discontinuities than loss.

In the coming decade we’ll likely see better optimization of connector impedances.  As this happens, concerns over RL and IL might become more balanced.  However, I will continue to slant my efforts towards managing RL until SerDes compensate for RL as well as they compensate for IL.  And speaking of IL, be careful when a connector’s datasheet derives its data rate from the -3dB point on the connector’s insertion loss plot.  It seems unreasonable to me that a component occupying less than a tenth of the interconnect would claim 30% of its loss – particularly when the connector presents discontinuities that limit its data rate to something lower. 

Now that we’ve examined the colorful world of connectors, let’s have a look at IC packages. 

Unwrapping the Package

From the beginning of IBIS the relevance of an IC’s Package has always been acknowledged and modeled.  We began with a lumped RLC model, which could be defined either globally for the entire package or uniquely for each pin.  [Pin Mapping] was added in IBIS 2.0 to enable SSO (Simultaneous Switching Output) simulation, mapping IO pins and models onto their respective power busses.  As higher frequencies came along, we learned to sub-divide our RLCs into smaller lumps or use transmission line models for better accuracy.  In this era of large 14nH bond-wires I even tried to patent inadvertent package crosstalk; it made a pretty good oscillator if you buffered it right.  Indeed, package effects are relevant. 

Perhaps due to its position at the boundary between the IC and System, the development of package modeling – which now also includes die-level interconnect – has been one of the most challenging projects the IBIS Standard has addressed.  An alphabet soup of standards (ICM, ISS, Touchstone), matrices, and committees brought us to BIRD 189.7 and IBIS 7.0.  This revision of IBIS brings the promise of capturing, modeling and automating the complexities of modern IC packages for next-generation SI analysis.  I appreciate the industry’s effort to improve package models; it has not been a subject for the faint of heart.

Simulating serial links over the past decade I’ve been content to integrate the IC vendor’s 4-port S-Parameter (.s4p) models of the package’s diff-pairs into my analysis.  I’ll go looking for these models if I don’t readily see them with the SerDes model, sometimes finding them in a sub-directory or download I may have missed.  As with connector characteristics, package parasitics are converging to more consistent impedances, with small (unavoidable?) discontinuities for the blips, bumps, or balls the signals must traverse.  In general the modern package’s parasitics help isolate and improve RL (Return Loss) problems similar to the way PCB routes do for connector discontinuities. 

In Conclusion

Connectors and Packages are unavoidable in electronic systems, and their models occupy an important place in any SI simulation.  Characterization, modeling and design improvements have been an iterative and relevant engineering challenge for some time, and new formats and techniques continue to improve accuracy.  Discontinuities in the journey and the components themselves are smoothing out, while higher data rates increase the relevance of the same.  In practice, the industry and SI Engineers continue to demand higher performance.  We wouldn’t have it any other way. 
Donald Telian, SiGuys - Guest Blogger 12/9/2019

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