Author: Donald Telian, SI Guys - Guest Blogger
The way high-speed signals interact with trace impedance has
changed a bit over time, making the subject worthy of our attention.
Thankfully, the importance - and even
mechanics - of proper trace impedance is widely understood and agreed
So much so, the concept almost
seems mundane – particularly against the rising importance of proper
have found that engineers can benefit by improving their trace impedance
For example if my trace
impedance is low, should I make my trace thinner or wider?
And if I can’t do that, should I move it
closer to or further from ground?
single-ended and differential signals interact with trace impedance in the same
Let’s have a look.
Capacitance and Impedance
Impedance intuition is readily acquired through two simple
equations. Trace impedance “Z” is
directly related to trace inductance (L) and capacitance (C), or Z=sqrt(L/C). While I’ve met a few who prefer to look at
things inductively, the majority of us find capacitance simpler to grasp. In the realm of PCB traces, the terms in the common
approximation for Capacitance (C=εA/d) are easily transferred to trace
construction and simple to visualize. In
the equation, “d” is a trace’s distance to ground, “A” is the area or size of
the trace (i.e., its width), and “ε” is the dielectric constant of the
surrounding material. Keeping this
equation in mind impedance intuition follows, allowing you to predict the
effects physical changes will have on impedance. Just keep in mind the inverse relationship
between capacitance and impedance. In
other words, as “C” goes up “Z” goes down, and vice versa.
So let’s try a few examples.
Say I need to make traces thinner to route through a dense area, will
the impedance go up or down? In this
case “A” decreases causing “C” to decrease as well, resulting in an increase in
“Z” or a higher impedance. Or what if
production wants to swap in some modern materials that have a lower dielectric
constant “ε”? Once again, capacitance
goes down so impedance goes up. As both
these common occurrences have raised impedance, is there something I can do in
the stackup to lower impedance back to where I want it? You guessed it, manipulate “d” which is the trace’s
distance to ground. Indeed, if I decrease
“d” then “C” increases causing “Z” to go down.
See how that works? If you keep
the capacitance equation around, it will be simpler to keep an eye on
maintaining trace impedance when you trade-off common PCB parameters.
Taking the capacitance equation (C=εA/d) forward, we might
expect trace impedance to scale inversely with dielectric constant “ε” if we hold
the ratio of trace width and distance to ground constant (A/d). Figure 1 shows this is generally true. Spanning the range of common dielectric
constants (on the X axis), we note that trace impedance (on the Y axis)
decreases ~linearly. The upper cluster
of lines are microstrip (outer layer trace, ground on one side) impedances,
varied by constant H=W (Height=Width, or d=A) values in mils. The lower cluster shows stripline (inner
layer trace, grounds on both sides, hence two heights “H”) impedances, again
with a constant A/d ratio.
Figure 1: How Trace Impedance Scales with Dielectric
Today’s high-speed designs primarily use 50 Ohm stripline
traces. Figure 1 shows this is easily
achieved with modern dielectric constants of ~3.5 for nearly all heights and
widths. Since all lines straddle 50
Ohms, minor parameter adjustments will easily bring almost any stripline PCB
construction to your target impedance value.
Try it yourself with this stripline
Figure 1 also reveals that microstrip traces are not as
amenable to 50 Ohms. That’s not too
problematic because the use of microstrip is decreasing; it is primarily used
for short connections from components to vias.
Long microstrip routes are avoided for a variety of reasons, such
- Component density leaves little room for routing on outer layers
- Fabrication parameters such as pre-preg thickness and etch angle are harder to control
- Noise radiating from outer layer traces is not shielded by ground
As serial links became the high-speed interconnect of
choice, PCB traces became predominately “differential”. In practice, signal connections now required
two routes instead of one; and that changes the impedance situation a bit. Furthermore, there are some differences in
how trace impedance interacts with differential and/or single-ended signaling
we need to be aware of.
Differential traces came into the mainstream for a number of
good reasons. If you think about it, all
signals are in a sense “differential”, because the logic level they transmit is
always referenced to something – typically “ground”. As voltage swings decreased and “ground”
became less consistent between components, PCBs, and systems, signals began to
carry their own reference – or the other side of a differential “pair”. At the same time, single-ended signals became
more fragile as the criticality and complexity of their design escalated and
their margin to “reference” eroded.
Other reasons typically cited for differential signaling are
decreases in crosstalk, power/ground rail noise, and EMI. Some of these attributes relate to the fact
that a diff-pair often couples more to itself then its ground reference and/or
neighboring signals – although some diff-pairs are implemented with wide gaps
making them uncoupled or loosely coupled.
And differential pairs are certainly better for long-distance
The differential impedance of an uncoupled diff-pair is two
times the trace’s single-ended impedance, and is typically specified to be 100
Ohms or 85 Ohms. Impedance-wise, the
thing to remember is that as spacing between the pair decreases the
differential impedance also decreases.
One way to think about that is to picture coupling increasing, increasing
capacitance (“d” in C=eA/d
decreasing), and hence impedance “Z” decreasing. This decrease can be substantial. For example, the differential impedance of 4
mil stripline traces with distant grounds can decrease 30 Ohms as the traces move
closer together. However in practice, a
10 Ohm decrease is more common.
PCB fabrication introduces a variety of factors that affect
trace impedance. Etch angle (the way fabricated
traces turn out to be trapezoids instead of rectangles) raises impedance
because “A” and hence “C” go down, causing “Z” to increase. Outer-layer plating (and hence etch angle)
and solder mask dielectric thicknesses vary as well – both issues causing more
change in impedances than you might think.
And the thickness of copper on your signal layers (½ ounce, 1 or 2
ounce) also affects impedance, albeit to a lesser degree.
Fiberglass weave effects, fabricator re-imaging, and
pre-preg thickness variation also significantly affect impedance. These effects are discussed in more detail here.
Impedance and Loss
Serial links have forced us to pay attention to high-frequency
loss in traces, while trace impedance gets set to a constant. Differential impedances typically target 100
Ohms, I’ve been amazed by how stable links perform across a wide range of trace
impedance – as long as impedance discontinuities are managed. Figure 2 shows how chip-to-chip 15 Gbps
channel performance is influenced primarily by loss, or the choice of a dielectric
material’s Dissipation factor “Df” (red=0.2, blue=0.1, green=0.002 – sometimes
called “loss tangent”). Even though the
Tx and Rx impedances are 100 Ohms, eye heights (Y axis) are shown to almost
constant against a +/- 20% tolerance in trace impedance (X axis). More impactful are material choices, which cause
a 4x (blue) to 6x (green) increase in eye heights – even without any Tx or Rx equalization. Applying 30% Tx de-emphasis improves Df=0.2
performance 3x (light red, X markers) with no material change, demonstrating
power of SerDes Equalization Settings, or SES.
Figure 2: 15 Gbps Eye Heights, Varying Trace Impedance
and Dielectric Loss
To emphasize the relevance of material loss the channel used
in Figure 2 had constant impedance, as might occur in a simple chip-to-chip
connection of about 7”. As such, the
only discontinuities occurred at the chip boundaries. Note that channel impedance
discontinuities must be carefully managed to realize Figure 2’s
immunity to trace impedance. In practice
this can be difficult, however – depending on data rate – some
discontinuities can be ignored.
Though differential serial links show some immunity to trace
impedance, the relevance of trace impedance to proper voltage swings in single-ended
signaling schemes (such as DDRx) cannot be overstated. Indeed, this is the dynamic that forced us to
get good at modeling, designing and fabricating PCB traces 30 years ago. So whether you are managing discontinuities
in serial links, or buffer/trace impedance trade-offs in DDRx, a working
knowledge of trace impedance is essential; which brings us back to the importance
of understanding PCB trace impedance, in practice.
While the concept of trace impedance has been with us
throughout the digital signal integrity journey, its interaction with signaling
schemes has changed somewhat. What
hasn’t changed is the mechanics of trace inductance and capacitance, and hence
impedance. Equation-based schemes to
visualize how impedance changes against physical parameters are helpful.
SiSoft users working with DDRx buffer/termination/trace
impedance choices can access a process and
QSI-ready Kit that illustrates how to maneuver through the
trade-offs, as well as more than a dozen implementation
Kits targeting common memory interfaces. There are also numerous
QCD-ready serial link Kits pre-configured to help you understand and
apply relevant specifications to your particular implementation.