# Understanding Via Impedance

**Why should I care?**

Serial links can fail because of impedance miss-matches (discontinuities). In practice, discontinuities are likely causing more problems than loss. While loss degrades a signal somewhat predictably and can be compensated by equalization, discontinuities cause reflections that are much harder to tame. So, fix the discontinuities and you fix the net. Here’s an example of a 400% eye improvement achieved by correcting via impedance (page 4) – a mere 1% of the interconnect. Also have a look at this method to improve via impedance (page 21), and its performance improvement measured in hardware.

Though they are small, vias can significantly impact performance. This first became apparent when ¼ wavelength stubs crept into systems. Did you know a via stub left in a ¼” thick backplane can completely remove a 12 Gbps signal? Per Eric Bogatin’s helpful approximation, 3/12 equals ¼” (yes, just use 3/Gbps and get inches). While stubs can be disastrous, as data rates increase via impedance miss-match is also increasingly problematic. But how can we better understand the impedance of vias?

**Enter Via modeling**

In the 1990s, while my RF friends were busy with exotic 3D solutions of vias, we would place a 0.5pF capacitor in our interconnect model at via locations and call it good. Over time, we learned that modeling vias as a transmission lines is a better approach. SiSoft tools implement a fast via solver (page 4) that expands on the transmission line concept to deliver correlated accuracy, as described in this paper. Yet even if you don’t have access to a fast via solver it’s possible to gain an intuitive sense of via impedance, as described below.

**Building Impedance Intuition**

To build our intuition on what via dimensions will yield impedances we want, let’s begin with the more familiar differential trace shown in Figure 1. Indeed, vias behave a bit like traces – albeit in the Z dimension. Figure 1 shows stripline trace impedance versus width, spacing, and distance from ground planes (X axis represents W=S=H1=H2 per the cross-section view). Interestingly all dimensions yield impedances close to what we typically want, and minor adjustments are used to dial in the value more precisely. For example, increasing either or both of the H values moves the reference plane further away making the trace more inductive thus raising the impedance (Z=sqrt[L/C]), while widening the trace (W) makes the trace more capacitive thus lowering its impedance. Visualize how these two changes impact impedance, because we’re about to apply them to via structures.

**Figure 1: Differential Trace Impedances**

Figure 2 plots differential via impedance versus common drill sizes on the X axis. Pad sizes are drill+10 mils and antipad sizes are drill+20 mils (8 mil drill dimensions in the example via solution overlay). Spacing is 1 mm as would be found under a BGA or near a connector. The first thing we notice is the range of impedances has increased more than 4x when compared to the trace impedances of Figure 1. This wider range makes via impedance more challenging to dial in. Like traces, we can make changes to a via’s structure to adjust its impedance. For example, widening the antipads – or even connecting them into an oval “racetrack” shape – moves the reference plane further away (similar to increasing trace H in Figure 1) making the via barrel more inductive thus raising its impedance, while increasing the drill size widens the barrel (similar to increasing trace W) making it more capacitive hence lowering its impedance.

**Figure 2: Differential Via Impedances**

Again, the challenge with vias is the 4x+ impedance range compared to the narrower range associated with traces – seen clearly by comparing Figures 1 and 2. As structural adjustments for traces and vias have similar dimensions, they also have similar effects on impedance – perhaps 5 or 10 Ohms in either direction. As such it becomes difficult to get 16 or even 12 mil vias close to 100 Ohms because their “natural” (i.e., no structural modifications) impedances are ~70 Ohms. Thus it should become apparent why 8 mil drills are gaining in popularity in a world somewhat reluctant to move towards 85 Ohm impedance – which is the “natural” impedance of the more common 10 mil via.

**Digging Deeper**

You might be objecting to my generalizations because I did not state my dielectric constant (Dk). You’re right. It was 3.3, which you might get with some flavors of Megtron 6. Indeed, Dk proportionally raises capacitance and hence inversely affects impedance. As such, the first time I solved 10 mil vias in Tachyon®100 (Dk=3.0) I found them closer to 100 Ohms than expected. With common Dk values varying 50% (3.0 to 4.5), Dk is indeed an important consideration. So when use Figure 2, if your Dk is higher than 3.3 your impedance values will be lower and if your Dk is lower your impedances will be higher. For example as Dk ranges from 3.0 to 3.6, the Figure 2 impedances change +/- ~4 Ohms.

We should also discuss differential trace and via spacing. As traces or vias get closer together they become more capacitive and hence impedance decreases. While the trace impedances in Figure 1 can be increased ~10 Ohms by separating the traces, via impedances will decrease from those shown in Figure 2 as vias move closer together. However, due to their associated pads, via barrels cannot move closer together than ~20 mils making it difficult to decrease impedance by more than ~ 5 Ohms.

Also be advised that as we pass 28 Gbps NRZ we will likely need to stop thinking of vias as a single impedance, but instead as a structure whose impedance dips at the pads and rises in the barrel. A good topic for another post!

**In Conclusion**

As you start down the road of grappling with via impedances – and more tools and measurements become available for the same – the task will simplify, just as it did for traces. My goal has been to give you a reference point to make the task of implementing via impedances – and hence removing via impedance discontinuities – less daunting.

**About the Author**

Donald Telian is the Owner of SiGuys, and is an independent Signal Integrity Consultant. Building on over 30 years of SI experience at Intel, Cadence, HP, and others, his recent focus has been on helping customers correctly implement today’s Multi-GHz serial links. His customers now have tens of thousands of serial links in production spanning products from disk drives to cellular data routers. Donald is widely known as the SI designer of the PCI bus and the originator of IBIS modeling and has taught SI techniques to thousands of engineers in more than 15 countries.

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