Papers & Presentations
Multi-Gigabit Serial Link Analysis
- FEC Performance Estimation for High-Speed Serial Channels, DesignCon 2019
- Application of Pulse Response Extraction to Nonlinear Data Channels, DesignCon 2017
- The Challenges of Measuring PAM4 Signals, DesignCon 2016
- A Brief Tour of FEC for Serial Link Systems, Tutorial presented at DesignCon 2015
- Moving Higher Data Rate Serial Links into Production -Issues & Solutions, DesignCon 2014, DesignCon Best Paper
- Practical Method for Measuring Digital Driver Impedance, DesignCon 2014
- Applying Microwave Techniques to Digital Systems: A Simple Case Study, DesignCon 2013
-
- Spectrum Analyzer and High-Speed Data: An Odd Couple, EEWeb, October 2012
- Repeaters: Learn to Love 'Em, March 2012
- Simulating Large Systems with Thousands of Serial Links, DesignCon 2012
- Accuracy of the Computational Experiments called Time Domain Simulations, June 2011
- Studying Clock Recovery Performance Using IBIS-AMI Models - DesignCon 2011
- Using IBIS-AMI Models to Study Clock Recovery Loop Performance - Technical Paper, 2010
- Using IBIS-AMI Models to Study Clock Recovery Loop Performance - Poster Session, EPEPS, 2010
- Predicting BER with IBIS-AMI models (co-authored with IBM)- DesignCon 2010
- A Tale of Long Tails (co-authored with Huawei)- DesignCon 2010
- When Shorter Isn't Better (co-authored with Cray)- DesignCon 2010
- Multi-Gigabit Serial Link Analysis Using HSPICE and AMI models - SNUG 2009 Award Winner
- Comparison of BER Estimation Methods which Account for Crosstalk - DesignCon 2009
- Calculating Tap Weights - How to derive tap weights from a stated de-emphasis value.
- System-level Serial Link Analysis using IBIS-AMI Models - Shanghai & Tokyo IBIS Summits, Nov 2008
- Crosstalk Analysis of a System Based on XAUI HMZd Evaluation Backplane Data - EMC 2008
- Exploration of Deterministic Jitter Distributions - DesignCon 2008 Best Paper Nominee
- Multi-Gigabit Serial Link Analysis - Piecing Together a Design and Verification Strategy - SNUG Boston 2007
- An Engineering Hat Trick - DesignCon TecPanel, 2007
High Speed Parallel Interface Analysis
Simulation Modeling
- Design & Development of DDR5 IBIS-AMI Models, DesignCon 2019
- Applying IBIS-AMI Techniques to DDR4/5 Analysis, DesignCon 2018
- Building IBIS-AMI Models for DDR5 Applications, DesignCon 2018
- Intro to IBIS-AMI Tutorial, DesignCon 2018
- A Beginner's Guide to SerDes AMI Modeling, DesignCon 2017
- IBIS-AMI: Assumptions, Terminology & Analytical Flows, IBIS Summit, DesignCon 2017
- Accurate AMI Analysis - Whose Responsibility Is It?, DesignCon 2016
- Two for One: Leveraging SerDes Flows for AMI Model Development, DesignCon 2016
- Building IBIS-AMI Models from Datasheet Specifications, DesignCon 2016
- Getting Street-Smart about S-Parameters, DesignCon 2015
- Understanding IBIS-AMI Simulations, DesignCon 2015
- How Design of Experiments Saved My CEI VSR 28G Design, DesignCon 2014
- Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies, DesignCon 2014
- High-Speed Boards Need Automated Checking, The PCB Design Magazine, February 2013
- Measurement-based Simulation: Increasing IBIS-AMI Model Accuracy with Data from Lab Measurements: DesignCon 2013
- TDR:Reading the Tea Leaves, June 2012
- Example Test Bench (Download) from DesignCon Tutorial, AMI Models: How to Tell a Peach from a Lemon
- AMI Models: How to Tell a Peach from a Lemon (pdf)
- What Bumblebees and Models of DFE Have in Common
- The Long and the Short of Vias, October 2011
- SParameter Causality: A Sampled Data Perspective
- Modeling Analog Repeaters in IBIS-AMI, DesignCon IBIS Summit, February 2011
- AMI Backchannel Co-Optimization - DesignCon IBIS Summit, February 2011
- Experiences Correlating IBIS-AMI Models and Measurement - DesignCon IBIS Summit, Feb 2010
- What's a Smith Chart? - Jan 2010
- Scaling Impulse/Pulse responses calculated via DFT - Jan 2010
- Converting between Voltage or Power and dB - July 2009
- S Parameter Reference Nodes - July 2009
- A Simple Via Experiment - DesignCon 2009 Best Paper Award
- Q & A on "A Simple Via Experiment"
- Creating Broadband Analog Models for SerDes Applications - DesignCon 2009 IBIS Summit, Feb 2009
- Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard - DesignCon 2008 Best Paper Nominee
- SiSoft's IBIS-AMI Model Evaluation Toolkit - Beijing & Tokyo IBIS Summits, Sept 2007
- IBIS-AMI Modeling Proposal Status Report - Beijing & Tokyo IBIS Summits, Sept 2007
- IBIS-ATM Model Validation - IBIS-ATM task group, July 2007
- IBIS-ATM SerDes Modeling Status Report - DAC IBIS Summit, 2007
- IBIS-ATM Modeling Proposal - DesignCon IBIS Summit, 2007
- IBIS-ATM SerDes Modeling Status Report - DesignCon IBIS Summit, 2007
- Serial Link Modeling Terminology - IBIS-ATM Sub-committee, 2006
- System Level Timing Closure using IBIS Models - Shanghai/Tokyo IBIS Summits, 2006
- Can IBIS Accurately Model SSO? - IBIS Summit Oct, 2004
- IBIS Quality Committee Update - IBIS Summit June 2003
- Practical Use of IBIS Quality Checklist - IBIS Summit January 2003
- IBIS Quality Committee Report - IBIS Summit October 2002
- SPICE versus IBIS - IBIS Summit October 2002
- IBIS Quality Committee Report - IBIS Summit June 2002
- LVDS IBIS Models @ 1.25GHz - IBIS Summit June 2003
- Improving IBIS Quality - DesignCon 2002
- The Bitter-Sweet Experiences of Using IBIS Models - IBIS Summit January 2002