# Q & A for the Via Physics Webinar

**Question:**

I watched with great interest the replay of your webinar on vias, which unfortunately I was not able to participate in at the time. It was actually one of the most useful and practical webinars I have ever seen.

The concept of modeling vias in multilayer PCB’s as coaxial transmission lines is very appealing in its simplicity, but you didn't mention the question of where the line begins and ends.

For your experimental setup, the length of the line is clearly the thickness of the dielectric, but what about in a real PCB? There are usually no ground planes on signal trace layers, so does the via transmission line start where the via goes through the first plane, or where the trace meets the via?

The extreme case would be where a trace jumps two layers, eg from the layer 1(top) through layer 2 (ground) to layer 3. Maybe the part of the via between layer 1 and 3 is too short to model in this way, so we're only really concerned with the stub from layer 3 to be bottom side? Alternatively, would it be more realistic to think of the via as a continuous transmission line of length = the PCB thickness, with the traces connected to 'taps' spaced along it according to the vertical positions of the relevant tracking layers?

Any comments would be appreciated.

Answer:

*I'm glad you found our webinar useful, and thanks for the very good question. *

What I've been doing has been to start the virtual coax model at the point where the signal trace contacts the via barrel, and end it where the via barrel contacts the signal trace. I've also been assuming that the signal trace maintains its impedance all the way to the via barrel (even where it goes across the antipad), and so the length of the trace is from via barrel to via barrel. Both of these choices are approximations that almost guaranteed not to be perfectly accurate, and I don't have any good data to indicate how accurate or inaccurate they are; however, they look about right to me. For typical PCB dimensions, I would expect these approximations to be more than accurate enough for data rates at or below 10 Gb/s. By the time we get to 20 Gb/s, we may have to be more precise in our modeling of this structure.

I should add that when there are multiple connections to a via, or there is a stub extending from the nearest connection to the top or bottom of the board, I model each barrel segment between nearest connections or between the top/bottom connection and the top/bottom of the board as a separate virtual coax, using the port definitions I described in my previous e-mail.

**Discussion:**

In a subsequent exchange, this person recommended a solution for a round center conductor in a square shield. The URL is http://fermi.la.asu.edu/w9cf/articles/square/index.html.

Having visited this site, I can also recommend it as a nice result and an instructive demonstration of analytic technique.

**Question/Comment:**

I think the assumption that the wave reflects in phase at the edge of the cavity is not right. What I found in ESD measurements is that the wave hits the edge it reflects on both the top and the bottom of the metal. Some energy goes back in the cavity but equal energy goes on the top of the plate. It will then reflect off the coax, out of phase, back to the edge, back into the cavity, etc.

**Answer:**

*You ask an interesting question, and I can see where you're coming from. I'd like to know more about your ESD measurements because they would probably teach me a lot; but at least at this point I can't support your theory. *

First of all, the analysis I did assumed that all of the radial TEM energy was reflected in phase at the edge of the disk. You saw the correspondence between theory and measurement. Although it wasn't perfect, the remaining difference must divided between experimental error, conduction losses, some evanescent modes I haven't nailed down yet, and radiation losses. That doesn't leave a lot of room for radiation losses as a significant effect.

From an analytic point of view, it is quite true that there will be some sort of radiative mode at the edge of the disk. I haven't studied that particular chapter in my field solver very much, but since the dielectric thickness (0.062") is small relative to a wavelength for the frequencies measured, I would expect the impedance of that mode to be relatively high. My guess, unaided by calculation of any form, would be about 100 ohms. Conversely, the impedance of the outgoing or ingoing radial TEM wave at the edge of the disk is extremely low. That one I can calculate but haven't yet. What I can tell you, however, is that the impedance at the antipad boundary increases from zero at DC to about 10 ohms at 10 GHz. Given that the impedance will vary as approximately 1/r (first order guesstimate), that would be on the order of an eighth of an ohm at the periphery. Thus, one could calculate how the current will be divided between the ingoing radial TEM mode and the radiative mode (they're basically parallel resistors). That leaves maybe 0.1% or so of the energy being radiated. All guesswork at this point, but with a few days' effort I think I could dignify it with some closed form equations and calculated results. Taking inventory of my stock of round tuits, however, ... I am aware that ESD discharge is a very high bandwidth, high energy phenomenon, and I'm wondering what the dissipation mechanisms were in your measurements; so maybe all that affects are respective conclusions.

**Discussion:**

*Further exchange with the person who asked this question brought out the fact that they were doing an experimental study of the effects of ESD discharge on electronic systems. What they found was that there is a very strong, high frequency surface wave associated with the current flow from the ESD discharge, and this surface wave can couple to adjacent conductors even if the ESD current does not flow directly in those conductors. One conclusion is that unless the ESD currents are constrained to flow on the outside of an equipment shield, disruptions due to this phenomenon can be expected in conductors which are not shielded from the ESD event. *

->Look for an article on this subject in the June/July issue of Equipment Protection Magazine.

Although these surface waves definitely do exist, they did not affect the via measurements because they are much higher impedance than the radial TEM waves in the ground plane cavity. In order to affect the measurement, these surface waves would have to flow along the outside of the ground planes, along the outer surface of the coaxial shield, across the faceplate of the network analyzer, and back along the coax and ground plane on the other side. GROUND CURRENTS DON'T TAKE DETOURS.

**Question:**

What is the Effect of plane thickness (used only as GND ref plane/ return current path) on designs operating at 6 Gbps for a stripline construction.

Can 1/2 Oz. copper plane be used? How does skin depth effect this scenario.

Further, on the same question, if I have multiple GND planes of 1/2 oz then will it be ok from power deliver point to to have 1/2 oz copper?

**Answer:**

*Now that I have some time to look up a number and do a calculation, I can tell you that 0.5oz copper at room temperature is one skin depth thick at about 16 MHz and eight skin depths thick at 1 GHz. That should give you some sort of scale to go on. *

As far as power delivery goes, it depends entirely on the power density on your board. My direct experience is with boards that dissipate between 2.5kW and 3.5kW. At that power density, even with 2oz power planes, the PC boards themselves got really warm.

Here's an easy way to make a first estimate: The DC resistance of 0.5oz copper at room temperature is about 1 milli-ohm/square. So, for example, if you have a 1.2V power converter dedicated to power a single high performance microprocessor (say, 100 Watts dissipated), then there will be around one square of plane between the power converter and the processor, resulting in an 83 mV drop from converter to processor for the voltage side and another 83 mV drop for the ground return, or 14 watts of power dissipation. That's a 14% loss of power conversion efficiency, which seems high to me. I would be looking for more like 2%. However, if the processor dissipation is 25 Watts rather than 100 Watts, that might be OK.

If there are multiple loads for each power converter or the path from the power converter to the loads is long and skinny for some reason, that will also need to be taken into account. To a first order, partition the planes from the power converter to each load so that, at least in your imagination, no two loads share any plane area between themselves and the power converter. How many squares long is each path now? For each path, multiply the number of squares by 1 milli-ohm to get its resistance. How much power will be dissipated getting to each load? When you add all that dissipation together, is the result acceptable? Clearly, multiple planes connected in parallel to carry the current would also help.

In short, what you conclude will depend on the total current to be supplied. For 2.5 kW at 1.2V, you'll quickly conclude that there's No Feasible Way the design could depend on 0.5oz power planes. For 25W to a single load, 0.5oz copper might be perfectly OK.