December 2020- TechNeeks
in
Newsletters
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12/17/2020
COM | LPDDR5 Architectural Kit | PCIe Gen5 Kit Updated | Via Impedance | AC Coupling/DC Blocking Capacitors | QCD's AMI Models
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November 2020 - TechNeeks
in
Newsletters
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11/19/2020
COM, QCD, IC's and Systems | LPDDR4 or 4x | QSI Widebus Crosstalk Videos and Kit | High-Speed=Serial Links | Eyes, Masks, Contours and BER's, | QCD and SiViewer Demo Videos
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October 2020 - TechNeeks
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Newsletters
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10/29/2020
Crosstalk Scan Video | Advanced DDR4/5 Analysis | Using SerDes S-Parameter Data | Fixing SI Issues in Software | PCIe Gen5 Analysis Kit | Understanding Loss/Inch in PCB Traces
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September 2020 - TechNeeks
in
Newsletters
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09/29/2020
QSI Timing Videos | How to Quickly Configure AMI Models | QSI Widebus Video Series | PCIe Gen5, 32 Gbps NRZ Design Kit | COM Simulation in QCD
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August 2020 - TechNeeks
in
Newsletters
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08/28/2020
PCIe-Gen5, Using S-Parameters in QSI, Compliance Mask Creation Video, Finding Trends in Scatter Plots, Simulating a Serial, Link, New COM features and video series
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July 2020 - TechNeeks
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Newsletters
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07/23/2020
New COM features and video series, Managing Loss and Discontinuities, Building AMI Models from Datasheet Specs, FREE book on SI, Using TDR to Improve your Design, Updated Design Kits
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June 2020 - TechNeeks
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Newsletters
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06/19/2020
QSI DDRx Kits; QSI STAT Mode Videos; PCB Materials vs. Frequency; Signal Integrity, Then and Now; Thinking about Power Integrity; A Plot is Worth 1,000 Waverforms
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May 2020 - TechNeeks
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Newsletters
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05/22/2020
QSI Widebus Example Kit, 100GBASE-KR (IEEE 802.3bj) Kit, Simulation / Measurement Correlation, Checking your pulse (response), Hula Hoops and Unit Intervals, Why Serial Links?
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April 2020 - TechNeeks
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Newsletters
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04/20/2020
QSI Widebus Example; Simulators, Models and the Next Great Thing; DFE and Bumblebees; Serial Link Equalization Made Simple; and How to Configure SiSoft’s Advanced SerDes Model to Match your Device Specs.
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March 2020 - TechNeeks
in
Newsletters
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03/20/2020
Simulating Serial Link Compliance, Simulating with Hspice Buffer Models, Automated Checking: PCB Layout, FFE vs. CTLE vs. DFE, Understanding PCB Trace Impedance and The Taming of the Slew (slew rate derating)
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