March 2020 - TechNeeks
in Newsletters - 03/20/2020
Simulating Serial Link Compliance, Simulating with Hspice Buffer Models, Automated Checking: PCB Layout, FFE vs. CTLE vs. DFE, Understanding PCB Trace Impedance and The Taming of the Slew (slew rate derating)

February 2020 - TechNeeks
in Newsletters - 02/22/2020
DesignCon 2020 AMI Panel, Latest Software releases, Sweeping Trace and Via Models in Pre-layout., DDRx Memory Interfacing, Next-gen AMI and SerDes Toolbox, Signal Integrity's Soft Skills, and Finding Trends in Scatter Plots

January 2020 - TechNeeks
in Newsletters - 02/21/2020
Serial Link Equalization Primer, QSI Widebus Crosstalk, Download Free Book on Signal Integrity, Table-driven Loss Models, Dk/Df vs Frequency

December 2019 - TechNeeks
in Newsletters - 12/19/2019
Understanding Connector and Package Impedance, Generating IBIS-AMI Models from your SerDes Design Workflow, Managing Loss in the Next Decade, and Using Rules Files to customize Transfer Nets.

November 2019 - TechNeeks
in Newsletters - 11/19/2019
Exercising engineering judgement, configuring SiSoft's advanced SerDes model, checking your pulse response rate, updating your design kits, how you can fix signal integrity issues in software and Smith charts.

SiSoft at DesignCon 2020
in Events & Conferences - 10/31/2019

October 2019 - TechNeeks
in Newsletters - 10/24/2019
Work WITH your Layout Engineer, QSI Crosstalk Video Series, Data Mining, Technical Paper on Repeaters, Simulating Serial Links, 100GBASE-KR (802.3bj) Kit.

September 2019 - TechNeeks
in Newsletters - 09/19/2019
Relevant Feature Size (which lengths to model and design carefully), Using Kits to automate compliance, Automate Loss/Eye Masks and Measurements, How to Length Match above 10 Gbps, PCB Materials vs. Frequency, DesignCon 2020.

August 2019 - TechNeeks
in Newsletters - 08/15/2019
What is Signal Integrity, S-parameters, 7 Steps to Successful Serial Link Layout, Improving your design with TDR, AC Coupling / DC Blocking Capacitors, QSI DDRx Kits.

July 2019 - TechNeeks
in Newsletters - 07/16/2019
History of IBIS, Simulating with HSPICE Buffer Models, Using Design of Experiments (DOE) to trim analysis time from weeks to hours, PCIe Gen 4 Design Kit, Managing PCB Crosstalk, Latest Software release.