January 30 - February 2, 2012
Santa Clara Convention Center
Santa Clara, CA
Booth #100

Go Virtual with SiSoft at DesignCon!

We're Talking about Virtual Prototype Analysis.

Virtual Prototype Analysis (VPA) is a structured methodology for system-level signal integrity analysis. Benefits include an accelerated design cycle, increased design performance, improved design reliability and improved control over design manufacturing costs. Come by Booth 100 and see why VPA should be part of your design cycle.

Exhibtion Hours:
Tuesday, January 31, 2012 - 12:30 PM - 6:00 PM
Wednesday, February 1, 2012 - 12:30 PM - 6:00 PM

Click Here to Register for a Free Exhibit Pass or to Receive a 20% Discount on Conference Registration.

Conference Highlights:

AMI Models: How to Tell a Peach from a Lemon

Speakers: Michael Steinberger and Todd Westerhoff
Day / Time / Location: Monday 1:30- 4:30 Ballroom E,
Track / Format: High-Speed Serial Design / Half-Day Tutorial
Audience Level: Intermediate

Description: Most vendors now supply IBIS-AMI models of their SerDes macros. However, the accuracy, usability, and speed of execution of these models varies widely in ways that are not immediately obvious to many users. Using real models from un-named vendors and software tools that are publicly available free of charge, this tutorial demonstrates specific desirable and undesirable model characteristics, how they affect the user, and how to test or inspect for them.

(Eligible Passes: 1-Day Tutorial Pass (Monday), 4-Day Conference Pass (Mon-Thurs). 

To learn more about IBIS-AMI Models, visit SiSoft eLearning.

For more information, download the IBIS-AMI Info Sheet.

Simulating Large Systems with Thousands of Serial Links

Speakers: Walter Katz (SiSoft), Donald Telian (SiGuys), Sergio Camerlo (Ericsson) and Barry Katz (SiSoft)
Day / Time / Location: Wednesday 10:15-10:55 Great America K, 
Track / Format: High-Speed Serial Design / 40-Minute Technical Paper Session
Audience Level: Intermediate

Description: While not long ago a serial link was only a couple of wires, it's now becoming common for systems to including hundreds - and even thousands - of such links. This session describes the development and analysis of a large system with thousands of serial links. Due to the system's size and complexity, the design team invested in a multi-year effort to build and qualify a virtual environment capable of both verifying connectivity and simulating any and all of the channels. Problematic channels with incomplete system-level connections, poor eye openings, or high BER are quickly identified. Performance limiters such as inherent discontinuities, cavity resonances, and Tx/Rx equalization imbalance are found and examined in detail. The virtual system is also used to guide design choices such as layer stacking, via construction, back-drilling, and trace/connector impedances. Processes to optimize and select equalization choices are also described.

For more info, Contact Us Now.