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SiSoft Announces Tools for SerDes Model Evaluation and Development
SiSoft Announces Tools for SerDes Model Evaluation and Development
MAYNARD, Mass. - July 19, 2007 - Signal Integrity Software, Inc. (SiSoft™) announced plans to distribute an IBIS-ATM Evaluation Toolkit that allows interested parties to evaluate and develop models based on the proposed IBIS-ATM standard for SerDes modeling and channel analysis. This toolkit will include a "simulator" utility that allows IBIS-ATM models to be run as standalone executables, a fully functional SerDes transmitter model, documentation and a sample set of analysis data. These are the first tools and models to become publicly available as part of the proposed standard.
The toolkit will serve four important functions:
- Allow users to run sample simulations using the included transmitter model, assessing the impact of transmit equalization on channel behavior. Users will also be able to analyze receiver behavior by providing additional models.
- Provide a "reference implementation" for the simulator/model interface defined in the IBIS-ATM proposal. This will allow users experiencing problems with a particular EDA tool / model combination to assess the source of the problem.
- Allow IBIS-ATM model developers to develop and test models in a controlled environment. The "simulator" utility can also be used to document a model's intended behavior and produce a set of reference results.
- Provide a starting point for model development. The transmitter model in the toolkit will include source code that model developers can leverage to develop their own device-specific models.
"Effective analysis of serial links requires simulating millions of bits' worth of data", noted Dr. Michael Steinberger, lead architect for SiSoft's serial link analysis solutions. "IBIS-ATM models make this possible, providing simulation results that allow designers to evaluate critical design tradeoffs. We've seen simulation performance on the order of 1 million bits per minute, and demonstrated that these models can scale to simulations of 1 billion bits and beyond."
"We're enthusiastic about the IBIS-ATM standard", said Todd Westerhoff, SiSoft's vice-president of software products. "We believe this toolkit will allow designers to demonstrate the benefits of IBIS-ATM models for themselves, and serve as a starting point for vendors who want to develop their own models."
SiSoft is asking other members of the IBIS-ATM task group to review the kit before general release, to help assess current EDA tool and model interoperability. SiSoft will turn over ownership of the toolkit to the IBIS Open Forum as part of the formal standardization process later this year, allowing the toolkit to become the "golden" reference platform.
SiSoft is the leading provider of integrated timing and signal integrity solutions for high-speed digital system design. SiSoft's Quantum-SI™ products allow users to rapidly determine interface operating margins and achieve High-Speed Design Closure™, providing unprecedented accuracy in predicting system-level noise and timing margins.
SiSoft ensures its tools remain at the forefront of high-speed design by providing advanced high-speed consulting services including model development, I/O characterization, package design/analysis and system-level interconnect analysis. SiSoft design consultants utilize SiSoft's own commercial software to address some of the industry's most demanding design problems, helping ensure software product quality and functionality.
For more information, please visit www.sisoft.com or contact email@example.com
More information on the IBIS-ATM Evaluation Toolkit
(including sample simulation results) can be found on the IBIS-ATM task group's website
SiSoft is a trademark of Signal Integrity Software, Inc. All other trademarks are the property of their respective owners.
About SerDes Modeling and IBIS-ATM
Most high-speed serial links transmit both clock and data signals over a differential signal pair. At the receiver, the transmit clock is reconstructed from the data signal, thus reducing the number of signal conductors required and achieving accurate clock to data timing. They are becoming increasingly popular in system designs because they reduce device pin count and mitigate noise problems associated with single ended signaling. As serial link speeds increase beyond 3 Gb/s, signal quality deteriorates and active signal-conditioning techniques are needed to recover a usable signal at the receiver. There are currently no standards for modeling SerDes transmit / receive equalization and clock recovery behavior. Designers performing SerDes device simulations typically use proprietary IP vendor modeling tools, or methodologies and models developed in-house by the users themselves.
The IBIS Advanced Technology Modeling (IBIS-ATM) task group has been working since 2006 to define an industry standard for modeling SerDes equalization and clock recovery. The standard must support interoperability - allowing a set of models to run across multiple EDA platforms and allowing SerDes models from different IP vendors to run together in the same simulation. The standard must also protect semiconductor vendor IP, effectively modeling device-specific algorithms without revealing implementation details.
Members of the IBIS-ATM task group include:
- Agilent Technologies Inc.
- Cadence Design Systems, Inc.
- Mentor Graphics Corporation
- Signal Integrity Software, Inc. (SiSoft)
- Intel Corporation
- Micron Technology, Inc.
- Texas Instruments Incorporated
- Teraspeed Consulting Group LLC
The proposed IBIS-ATM standard defines a “black box” method for modeling SerDes devices where the models are implemented as executable computer code. The standard defines the mechanism for loading and executing the models, a standard format for model input/output data and an additional format for any model-specific parameters. This approach allows the model developer to use whatever language is most appropriate for the model at hand – the resulting code merely needs to conform to the defined conventions for how arguments and data are passed to/from the model.
The proposed standard supports modeling of both linear and nonlinear equalization techniques. Equalizers can additionally be modeled as either time-invariant or exhibiting time-varying behavior, allowing designers to evaluate equalizer sensitivity to specific pattern sequences. IBIS-ATM models can be used in conjunction with a variety of different analytical techniques, including time-domain and statistical analysis.
In June 2007, the IBIS-ATM task group approved a draft standard for prototype model and EDA tool implementations. These prototype implementations will be used to validate the fundamental premise of the effort: model interoperability between EDA tools and IP vendors with protection of semiconductor vendor IP. Refinements resulting from this process will be incorporated into an updated proposal before it is presented to the IBIS Open Forum later this year.
IBIS-ATM task group website