SiSoft Receives Best Paper Award Nomination at DesignCon 2009

2/24/2009

SiSoft Receives Best Paper Award Nomination at DesignCon 2009

"Simple Via Experiment” Named Best Paper Award Finalist in Board and Design Category

Maynard, MA – February 2, 2009 - Signal Integrity Software, Inc. (SiSoft™) today announced that its paper, “A Simple Via Experiment”, co-authored with Cisco Systems, has been nominated as a Best Paper Award Finalist at DesignCon 2009. The paper will be presented by Dr. Michael Steinberger, SiSoft, on Tuesday, February 3 in Track 5 of the Technical Program.

Vias play a critical role in the high frequency electrical behavior of packages and printed circuit boards, and thus have been the subject of intense study. The paper, “A Simple Via Experiment”, presents an analytical model for understanding and predicting the behavior of via structures that has been correlated to lab measurement. Theoretical, modeled (3-D field solver) and measured data will be presented for an experimental via structure which has been designed to make it easy for others to repeat the experiment.

“A Simple Via Experiment” contains closed form solutions to Maxwell’s equations, in addition to the computational solutions that specialists in the field have traditionally relied upon. This treatment provides not only a computation of the electrical behavior, but also a description of the current paths that will help engineers apply engineering judgment to via-related problems. The paper offers a back to basics approach that brings today’s designers back to their engineering roots.

SiSoft representatives will be demonstrating SiSoft products on the show floor during DesignCon. Conference participants will have the opportunity to see SiSoft’s product for serial link analysis, Quantum Channel Designer™, which combines high-performance simulation with IBIS-AMI SerDes modeling for the design and analysis of serial links up to 20 Gbps. Quantum Channel Designer uses a mixture of time-domain, frequency-domain and statistical techniques to accurately predict end-to-end BER of serial links.

Exhibition hours are from 12:30PM to 6:30PM on both Tuesday and Wednesday, February 3-4. If you are unable to attend DesignCon 2009 and would like additional information, please contact via email at: rkatz@sisoft.com or phone (978) 461-0449, x15.

About SiSoft™
SiSoft™ is the leading provider of integrated signal integrity and timing solutions for high-speed digital system design. SiSoft's latest product, Quantum Channel Designer™ (QCD), is a dedicated, system-level design and analysis environment for serial links up to 20 Gbps. QCD incorporates the latest frequency-domain, time-domain and statistical techniques to simulate the combined behavior of the passive channel and SerDes IP. Designers capture designs graphically, and then experiment with different physical layout and equalization strategies to predict how design tradeoffs affect operating margins and link Bit Error Rate (BER). Standards-based (IBIS-AMI) SerDes IP models provide the accuracy and performance required to meet the needs of serial link design.

SiSoft’s Quantum-SI™ products allow users to rapidly determine interface operating margins and achieve High-Speed Timing Closure™, providing unprecedented accuracy in predicting system-level noise and timing margins. Quantum-SI Interface Analysis Kits are pre-configured analysis setups for popular interface standards, such as DDR2 and DDR3, which encapsulate both interface architectures and design requirements to accelerate the high-speed design process.

SiSoft’s consulting services organization uses Quantum Channel Designer and Quantum-SI tools to provide advanced high-speed consulting services including IBIS model development, package design/analysis and system-level interconnect analysis -- ensuring that SiSoft’s signal integrity tools remain at the forefront of high-speed design.

More information on SiSoft can be found at www.sisoft.com.


SiSoft, Quantum-SI, Quantum Channel Designer, Core-to-Core, TransferNet, High-Speed Timing Closure and High-Speed Design Closure are trademarks of Signal Integrity Software, Inc. All other trademarks are the property of their respective owners.