Maynard, MA – January 29, 2009 - Signal Integrity Software, Inc. (SiSoft™) today announced that it will participate in a Technical Panel at DesignCon 2009 in Santa Clara on Power Distribution Planes. “We are very excited to be able to participate in the dialogue surrounding power distribution and share our expertise regarding the decision-making process designers must undertake when examining tradeoffs and determining whether or not to split distribution planes,” stated Barry Katz, president and CTO of SiSoft.
Dr. Micheal Steinberger, Distinguished Technical Staff Member, will be representing SiSoft on the Technical Panel. Dr. Steinberger has over 29 years experience in the design and analysis of very high speed electronic circuits. He holds a Ph.D. from the University of Southern California, and has been awarded 7 U.S. patents.
Monday, February 2 | 4:45 pm – 6:00 pm
SiSoft representatives will be demonstrating Quantum Channel Designer™ and Quantum-SI™ on the show floor at DesignCon in Santa Clara. Exhibition hours are from 12:30PM to 6:30PM on both Tuesday and Wednesday, February 3-4. If you are unable to attend DesignCon 2009 and would like additional information, please email email@example.com
or call me at (978) 461-0449, x15.About SiSoft™
SiSoft™ is the leading provider of integrated signal integrity and timing solutions for high-speed digital system design. SiSoft's latest product, Quantum Channel Designer™ (QCD)
, is a dedicated, system-level design and analysis environment for serial links up to 20 Gbps. QCD incorporates the latest frequency-domain, time-domain and statistical techniques to simulate the combined behavior of the passive channel and SerDes IP. Designers capture designs graphically, then experiment with different physical layout and equalization strategies to predict how design tradeoffs affect operating margins and link Bit Error Rate (BER). Standards-based (IBIS-AMI) SerDes IP models provide the accuracy and performance required to meet the needs of serial link design.
products allow users to rapidly determine interface operating margins and achieve High-Speed Timing Closure™, providing unprecedented accuracy in predicting system-level noise and timing margins. Quantum-SI Interface Analysis Kits are pre-configured analysis setups for popular interface standards, such as DDR2 and DDR3, which encapsulate both interface architectures and design requirements to accelerate the high-speed design process.
SiSoft’s consulting services
organization uses Quantum Channel Designer and Quantum-SI tools to provide advanced high-speed consulting services including IBIS model development, package design/analysis and system-level interconnect analysis -- ensuring that SiSoft’s signal integrity tools remain at the forefront of high-speed design. More information on SiSoft can be found at www.sisoft.com.
SiSoft, Quantum Channel Designer and Quantum-SI are trademarks of Signal Integrity Software, Inc.
Any other trademarks mentioned in this release are the property of their respective owners.