SiSoft at DesignCon 2019


SiSoft at DesignCon 2018
Conference: Jan 29-31, 2019
Expo: Jan 30 - Jan 31, 2019
Santa Clara, CA
Santa Clara Convention Center
Visit SiSoft in booth #935 and learn about exciting new developments in the area of signal integrity and SerDes design. We will be talking about design of DDR5 and PAM4 high-speed digital interconnects, using MATLAB for channel modelling, linking Simulink and QCD/QSI with IBIS-AMI model generation and more.

SiSoft Schedule

Papers / Presentations


Time: Wed. January 30, 11:05 AM - 11:45 AM | Mission City M1

Description: DDR5 is the next generation of high-speed DDRx memories expected to double the bandwidth of DDR4. To achieve these dramatic speed improvements, both controller and memory IO will need to adopt various equalization capabilities. These new features have required the model providers to adopt the capabilities of IBIS-AMI to properly model both the analog and equalization characteristics of the interface. This presentation will highlight key technology changes between DDR4 and DDR5, discuss the modeling environment requirements for time domain analysis, statistical analysis, and design regression, and finally describe the actual design and generation of IBIS-AMI DDR5 models.

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Time: Wed. January 30, 3:45 PM - 5:00 PM | Ballroom G

Description: Forward error correction (FEC) has been widely adopted by networking and storage systems. Recently its role has become more essential for high speed serial link transmission such as 56 Gbps and 112 Gbps per lane electrical and optical interfaces. In this panel a group of speakers from cross sections of industry will share their opinions, debate the issues, and provide solutions of FEC for high speed networking and storage serial link systems.

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Time: Thu. January 31, 3:45 PM - 5:00 PM | Ballroom D

Description: IBIS-AMI models are the ubiquitous choice for the most challenging simulation tasks, but which type of AMI model should I use when? What are their strengths and limitations? This year's AMI Panel examines vendor, template, library, spec, bit-stream/statistical and home-grown models, explaining the strengths and limitations of each. While the days of not having a model are over, what is the secret to succeeding amidst the myriad of options? Does the answer vary by application – particularly new applications such as DDR5? Join us for another insightful discussion to learn timely answers to these questions and more.

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Time: Friday, February 1, 2019, 08:00 AM to 5:00 PM

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