Modeling SerDes IP

Designers looking to model serial link behavior have traditionally faced difficult modeling and simulation problems. Traditional SPICE-based analysis isn't fast enough to simulate the millions of bits needed to adequately characterize link behavior. Dedicated simulation tools provided by SerDes IP vendors use advanced techniques to reduce simulation run times, but don't allow designers to model components from different vendors in the same simulation. Both system designers and SerDes IP providers have been seeking a new combined modeling/simulation methodology that can fulfill four critical requirements:
  • Performance - capable of simulating millions of bits within minutes
  • Interoperable - run SerDes IP models from different vendors in the same analysis
  • Transportable - single SerDes IP model that runs in multiple simulation environments
  • Accurate - detailed modeling of equalization and clock recovery behavior
Standardizing SerDes IP Models
Most proprietary SerDes simulation tools follow the same fundamental flow - the analog portion of the link is characterized, then that data is combined with equalization models and communication / signal processing techniques to predict the overall link response. Proprietary tools use a mixture of statistical and time-domain techniques to predict end-to-end link behavior. Many of these simulators employ algorithms based on techniques originally developed for RF/Microwave communications applications.
The IBIS Advanced Technology Modeling (IBIS-ATM) working group recognized that having a number of proprietary analysis tools using similar (but incompatible) modeling techniques presented an opportunity for standardization. The group solicited participation from key semiconductor, EDA and systems companies to define a standardized modeling and simulation strategy for high speed serial links. This resulted in the IBIS Algorithmic Modeling Interface (IBIS-AMI) specification, which defines a reference simulation flow for serial links and defines formal, standardized mechanisms for modeling SerDes equalization and clock recovery algorithms.
IBIS-AMI became part of the approved IBIS 5.0 standard in August 2008. IBIS-AMI model simulation allows SerDes IP providers to develop accurate, high-performance simulation models that can be used with any EDA platform that supports the IBIS-AMI simulation interface. Several major SerDes IP providers are already providing IBIS-AMI models for their devices, and SiSoft is working with others to bring more models on-line.

Repeater and Retimer Modeling
Repeaters and retimers allow designers to extend the electrical reach of their system enabling higher-performance on legacy backplanes. Quantum Channel Designer supports IBIS-AMI extensions that enable support of repeater and retimer simulations using IBIS-AMI models.


SiSoft is deeply committed to the success of IBIS and standards-based modeling. SiSoft has been a driving force behind the development and deployment of the IBIS-AMI model simulation specification, with contributions that include:
  • Co-authored the original standards (IBIS BIRDs 104 and 107)
  • First to release IBIS-AMI demonstration models and model development toolkit
  • First to demonstrate IBIS-AMI model interoperability First to develop and validate IBIS-AMI models under contract
  • First to present IBIS-AMI correlation to other simulation environments
  • First to present IBIS-AMI simulation performance data
  • First to release a fully IBIS-AMI compliant serial link design tool

Interested in knowing more about IBIS-AMI? We invite you to visit SiSoft's IBIS web page and the Official IBIS web site.