Design Analysis

Crosstalk Analysis

SiSoft's methodology is to determine crosstalk limits during the pre-layout phase of a design. This is accomplished through the use of coupled interconnect models whose signal spacing can be varied as part of the solution space analysis capability in Quantum-SI. The composite effects of signal integrity, timing, and crosstalk are captured. In post-layout, the Quantum-SI crosstalk scanner is employed to determine relative coupling metrics between signals on the entire design.
 
SiSoft's consultants set the scanner inputs for each signal type based upon group type, edge-rates, and voltage swings. The scanner allows fast extraction of crosstalk results and allows the designer to quickly converge on a solution. Based on these results, specific nets or entire busses can be simulated from the post-layout database to obtain exact crosstalk values as needed. Extraction of critical signals is performed and simulations are run in order to develop solutions to any crosstalk problems.
 

Timing Analysis

SiSoft works with our customers to understand the timing requirements of the system. Detailed timing models are then created for each device. The timing models created allow a detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous busses within a design. Eye diagrams are created to verify adherence to industry standard specifications, or for the validation of eye masks on clock recovery interfaces. System timing is analyzed and the implementation of PLL's and clock trees are accounted for. Setup and hold margins are calculated for every net, and since Quantum-SI allows integration of the signal integrity analysis and timing analysis, accurate trade offs between signal quality and timing can be made. The result is a system that is optimally tuned for operation.
 

Technology Assessments

SiSoft performs ASIC and system-level technology and architecture assessments. As part of these assessments, SiSoft assists its customers in developing detailed assessment plans to identify critical objectives, issues, an analysis approach, and deliverables. This includes a thorough review of proposed architectures and design documentation for critical system, packaging, connector, and ASIC technology. Once the design is understood, critical areas are identified for further detailed analysis. SiSoft's consultants create and validate required library models, prior to performing detailed simulations for each critical element. Once the analysis is complete, SiSoft generates a final report to document the analysis results, outstanding issues, and recommendations. A sample of the types of assessments include:
 
  • Comparison of industry foundry processes
  • Comparison of ASIC vendor capabilities
  • PCB laminates and wiring pitch
  • Implementation strategies
  • Package selection
  • Connector selection

Design Reviews

Signal Integrity Design Reviews
Sometimes having another set of eyes review a design will help flush out some design issues. SiSoft can act as this third party reviewer and help identify design issues. These reviews represent a low cost investment for our customer, but can result in high value as common design mistakes can be avoided. These reviews take a completed layout database and some of the items reviewed for include:
  • Power plane splits and decoupling
  • Signals crossing splits and antipads
  • Decoupling placement
  • Decoupling pad effectiveness
  • Stackup
  • Signal routing and return paths
  • Crosstalk potential
SiSoft provides a detailed report of our findings. These reviews have helped multiple customers stick to time critical schedules and reduce cost by reducing design iterations.
 

Design Kit Development

Design kits provide an out-of-the-box signal integrity, timing, and crosstalk analysis environment for performing pre-layout solutions space analysis and/or post-layout verification on targeted high-speed parallel buses and/or multi-gigabit serial links. SiSoft's experienced staff of signal integrity engineers will develop interface analysis kits to meet your requirements. These kits can be targeted for specific interfaces, ASICs, custom ICs, chip sets, FPGAs, or reference designs and leverage off the design analysis reuse capabilities of Quantum-SI.
 

Technical Staff

SiSoft's SI staff has a strong theoretical background in the SI arena, extensive practical experience, and diverse backgrounds from a wide area of design disciplines including:
 
  • Project management
  • System architecture
  • Custom IC design
  • ASIC design
  • Package design
  • Power Integrity
  • Microwave design
  • Connectors/Cabling
  • PCB technology
  • High-speed measurement
  • Simulation methodology
  • Modeling
These diverse backgrounds allow SiSoft to effectively identify the best solution to your design problems and have given us an unsurpassed record of first pass design success. In addition to the technical capabilities of our team, SiSoft has wide industry recognition. We have written a number of publications, are recognized speakers at both DesignCon and the IBIS Open Forum and are active participants in JEDEC.
 

Interface Experience

SiSoft consultants have designed a wide range of system interfaces including:
  • DDRI/DDRII
  • GDDRIII
  • PCI, PCI-X, PCI-Express
  • SATA1/SATA2
  • Hypertransport
  • AGP2x/4x/8x
  • RLDRAMI/RLDRAMII
  • Infiniband
  • SPI4
  • XAUI
  • Custom SerDes (2.5 Gbs->10Gbs)
Additionally, SiSoft's consultants have broad experience with microprocessor, Chipsets, and FPGA's from companies such as:
  • Intel
  • IBM
  • Motorola
  • Freescale
  • HP
  • VIA
  • Xilinx
  • Altera