BEGIN:VCALENDAR PRODID:-//Microsoft Corporation//Outlook 14.0 MIMEDIR//EN VERSION:2.0 METHOD:PUBLISH X-MS-OLK-FORCEINSPECTOROPEN:TRUE BEGIN:VTIMEZONE TZID:America/New_York BEGIN:STANDARD DTSTART:16011104T020000 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 END:STANDARD BEGIN:DAYLIGHT DTSTART:16010311T020000 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 END:DAYLIGHT END:VTIMEZONE BEGIN:VEVENT CLASS:PUBLIC CREATED:20130107T174738Z DESCRIPTION:http://www.designcon.com/santaclara/schedule-builder/session-id /259\n\nLocation:\nBallroom F\n\nDate:\nWednesday\, January 30\, 2013\n\nT ime:\n10:15 AM - 10:55 AM\n\nThe combination of a spectrum analyzer and sp ecific data patterns can be used to reliably identify different jitter and noise sources in SerDes transmitters and receivers\, quantifying the asso ciated impairments precisely. This paper uses data measured on a real syst em to explain the procedures for measuring clock-based DCD\, data-based DC D\, reference clock phase noise\, clock leakage\, power supply noise\, tra nsmission loss\, and crosstalk in the serial channels at the system level. Once the different impairments are quantified\, jitter and noise budgets are extracted that can be used by standard serial link simulation tools. T his allows data extracted from silicon characterization to be used to accu rately predict operating margins during new system design. This paper will demonstrate the derivation of device jitter and noise budgets along with the correlation of simulated results to the original measured data. \n\nS peakers: \nDr. Michael Steinberger\, Lead Architect of Serial Channel Prod ucts\, SiSoft \nPaul Wildes\, Principal Signal Integrity Engineer\, SiSoft \nAnders Ekholm\, Expert\, Signal Integrity and Timing Analysis\, Ericsson AB\nNicke Svee\, Hardware Designer\, Ericsson AB\n\n DTEND;TZID=America/New_York:20130130T135500 DTSTAMP:20130107T174534Z DTSTART;TZID=America/New_York:20130130T131500 LAST-MODIFIED:20130107T174738Z LOCATION:Ballroom F SEQUENCE:0 SUMMARY;LANGUAGE=en-us:Measurement-Based Simulation: Increasing IBIS-AMI Mo del Accuracy with Data from Lab Measurements TRANSP:OPAQUE UID:040000008200E00074C5B7101A82E0080000000060EDC6B5D3ECCD01000000000000000 010000000FBC3D717D73DB44DA5504BB3701A6AEA X-ALT-DESC;FMTTYPE=text/html:\n\n
\n\nhttp://www.designco
n.com/santaclara/schedule-builder/session-id/259
Location:
Ballroom F
\n\nDate:
\n\nWednesday\, January 30\, 2013< SPAN LANG="en-us">
\n\nTime:
\n\n10:15 AM - 10
:55 AM
The co mbination of a spectrum analyzer and specific data patterns can be used to reliably identify different jitter and noise sources in SerDes transmitte rs and receivers\, quantifying the associated impairments precisely. This paper uses data measured on a real system to explain the procedures for me asuring clock-based DCD\, data-based DCD\, reference clock phase noise\, c lock leakage\, power supply noise\, transmission loss\, and crosstalk in t he serial channels at the system level. Once the different impairments are quantified\, jitter and noise budgets are extracted that can be used by s tandard serial link simulation tools. This allows data extracted from sili con characterization to be used to accurately predict operating margins du ring new system design. This paper will demonstrate the derivation of devi ce jitter and noise budgets along with the correlation of simulated result s to the original measured data.
\n\nSpeakers:
Dr. Michael Steinberger\, Lead Architect of Serial Channel Products \, SiSoft
\n\n<
SPAN LANG="en-us">Pa
ul Wildes\, Principal Signal Integrity Engineer\, SiSoft
Nicke Svee\, Hardware Designer\, Ericsson AB
\n\n\n X-MICROSOFT-CDO-BUSYSTATUS:BUSY X-MICROSOFT-DISALLOW-COUNTER:FALSE BEGIN:VALARM TRIGGER:-PT15M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR